JPH0854418A - Trigger circuit - Google Patents

Abstract

PURPOSE:To realize a trigger circuit which prevents malfunction due to noise and the time delay of a trigger signal. CONSTITUTION:In the trigger circuit which generates trigger signals 110, 111 of an oscilloscope, a first comparator 2 to which an input signal 100 and a tigger level signal 101 are input, a second comparator 3 to which the input signal 100 and the trigger level signal 101 are input, a logic operation means 50 which operates the logical sum of outputs of the first and second comparators 2, 3 and a holding means 52 which holds the state of a trigger enable signal on the basis of the output timing of the logic operation means 50, are installed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trigger circuit used in a digital oscilloscope or the like, and more particularly to a trigger circuit that prevents false triggers due to noise and does not cause delay in trigger signals.

[0002]

2. Description of the Related Art A trigger circuit used in a digital oscilloscope or the like compares an input signal with a trigger level,
For example, a circuit that generates a trigger signal when the input signal exceeds the trigger level.

FIG. 3 is a circuit diagram showing an example of such a conventional trigger circuit. In FIG. 3, 1 is a comparator, 100
Is an input signal, 101 is a trigger level signal, and 102 is a trigger signal. Further, in this conventional example, the trigger signal 102 is output at the rising edge of the input signal 100.

The operation of the conventional example shown in FIG. 3 will be described with reference to FIG. FIG. 4 is a timing chart showing the operation of the conventional example shown in FIG. Further, "a" in FIG. 4 indicates the input signal 100, "b" in FIG. 4 indicates the trigger level signal 101, and (b) in FIG. 4 indicates the trigger signal 102.

As shown by "A" in FIG. 4, the input signal 100
When noise is superimposed on (b) Trigger signal 1
A waveform such as "d" in FIG. 4 is generated in 02, which causes a malfunction.

Therefore, in order to prevent such an erroneous operation, conventionally, the comparator 1 is provided with a hysteresis characteristic to prevent the generation of a waveform such as "d" in FIG. That is, by setting the hysteresis width as shown by "C" in FIG. 4, the waveform of the trigger signal as shown in FIG. 4C can be obtained. In the trigger signal shown in FIG. 4C, since there is no waveform corresponding to "d" in FIG. 4, malfunction can be prevented.

[0007]

However, in the conventional example shown in FIG. 3, when the comparator 1 has a hysteresis characteristic, malfunction due to noise can be prevented.
(F) The rising edge of the trigger signal (c) is delayed by the time shown in "to" in FIG. 4 as compared with "e" in FIG. 4 which is the actually desired rising timing. There is.

When such a time delay of the trigger signal occurs, the waveform originally intended to be observed may deviate from the screen range depending on the set value in the time axis direction. Therefore, an object of the present invention is to realize a trigger circuit capable of preventing malfunction due to noise and preventing time delay of a trigger signal.

[0009]

In order to achieve such an object, according to the present invention, a trigger circuit for generating a trigger signal of an oscilloscope is provided with a first comparator to which an input signal and a trigger level signal are input. A second comparator having a hysteresis characteristic to which the input signal and the trigger level signal are input, a logical operation means for calculating a logical sum of outputs of the first and second comparators, and the logical operation means Holding means for holding the state of the trigger enable signal on the basis of the output timing of 1.

[0010]

[Function] By holding the state of the trigger enable signal at the timing of the logical sum signal of the output of the comparator having no hysteresis characteristic and the output of the comparator having the hysteresis characteristic, malfunction due to noise can be prevented and the trigger It becomes possible to prevent the time delay of the signal.

[0011]

The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a circuit diagram showing an embodiment of a trigger circuit according to the present invention. Here, reference numerals 100 and 101 are the same as those in FIG. In FIG. 1, 2 is a normal comparator having no hysteresis characteristic, 3 is a comparator having hysteresis characteristic, 4 and 5 are OR circuits, and 6 and 7 are D-type flip-flop circuits (hereinafter, simply referred to as flip-flops). ).

Further, 103 and 105 are positive logic output signals of the comparators 2 and 3, respectively, and 104 and 106 are negative logic output signals of the comparators 2 and 3, respectively. In addition, 1
07 and 108 are output signals of the OR circuits 4 and 5 and 10
Reference numeral 9 is a trigger enable signal, and 110 and 111 are trigger signals.

Further, 4 and 5 are logical operation means 50,
Reference numerals 6 and 7 constitute holding means 51, respectively.

The input signal 100 is input to one input terminal of each of the comparators 2 and 3, and the trigger level signal 101 is input to the other input terminal of each of the comparators 2 and 3.

The positive logic output signals 103 and 105 of the comparators 2 and 3 are connected to the logical sum circuit 4, and the negative logic output signals 104 and 106 of the comparators 2 and 3 are connected to the logical sum circuit 5, respectively. The output signals 107 and 108 of the OR circuits 4 and 5 are connected to the clock input terminals of the flip-flops 6 and 7, respectively.

The trigger enable signal 109 is input to the data input terminals of the flip-flops 6 and 7, and the trigger signal 11 is output from the output terminals of the flip-flops 6 and 7.
0 and 111 are output.

The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. Here, FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG. Further, FIG. 2A is almost the same as FIG. 4A, and is different from FIG.
The middle "C" is the hysteresis width of the comparator 3.

Since the comparator 2 does not have a hysteresis characteristic, the positive logic output signal 103 has a waveform with a signal due to noise on both sides of the signal as shown in FIG. 2B. On the other hand, since the comparator 3 has a hysteresis characteristic, the positive logic output signal 105 has no noise signal as shown in FIG. However, there is a time delay as described above.

The logical sum circuit 4 outputs the output signal 107 having the waveform shown in FIG. 2D by taking the logical sum of the positive logic output signals 103 and 105. On the other hand, the logical sum circuit 5 outputs the output signal 108 having the waveform shown in FIG. 2E by taking the logical sum of the negative logic output signals 104 and 106.

Here, the trigger enable signal 109 is set to a high level after data acquisition is started and data for pre-trigger is acquired.

The flip-flops 6 and 7 output the output signal 10
By holding the state of the trigger enable signal 109 at the rising timings of 7 and 108,
A trigger signal as shown in (g) and (h) is output.

The trigger signals 110 and 111 are trigger signals at the rising edge and the falling edge of the input signal 100, respectively, and as can be seen from FIG. 2, the time delay unlike the conventional example does not occur. of course,
The trigger signals 110 and 111 are also unaffected by noise.

As a result, by holding the state of the trigger enable signal 109 at the timing of the logical sum signal of the output of the comparator 2 having no hysteresis characteristic and the output of the comparator 3 having the hysteresis characteristic, an error due to noise is generated. It is possible to prevent actuation and prevent a time delay of the trigger signal.

The trigger signals 110 and 111 are flip-flops 6 at the timing of the signal (waveform indicated by "d" in FIG. 4) generated due to noise among the signals of the output signal 103 or 104 of the comparator 2. Since 7 and 7 are held, the timing of the trigger signals 110 and 111 does not change even if the hysteresis width is changed.

Therefore, by increasing the hysteresis width in the comparator 3 to the extent that the amplitude of the input signal 100 is not exceeded, malfunctions can be prevented more reliably.

In the embodiment shown in FIG. 1, the input signal 10
The trigger signals 110 and 111 at the rising edge and the falling edge of 0 are output at the same time. However, when only one of the trigger signals needs to be output, the logical sum circuit 4 and the flip-flop 6 or the logical sum. It is possible to omit the circuit 5 and the flip-flop 7.

In this case, the comparators 2 and 3 may be comparators capable of outputting either a positive logic output signal or a negative logic output signal.

[0028]

As is apparent from the above description,
The present invention has the following effects. By holding the state of the trigger enable signal at the timing of the logical sum signal of the output of the comparator that does not have the hysteresis characteristic and the output of the comparator that has the hysteresis characteristic, malfunction due to noise is prevented, and the trigger signal time It is possible to realize a trigger circuit capable of preventing a dynamic delay.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a trigger circuit according to the present invention.

FIG. 2 is a timing diagram illustrating the operation of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing an example of a conventional trigger circuit.

FIG. 4 is a timing chart showing an operation and the like of the conventional example shown in FIG.

[Explanation of symbols]

 1, 2 and 3 Comparator 4,5 Logical sum circuit 6,7 D flip-flop circuit 50 Logical operation means 51 Holding means 100 Input signal 101 Trigger level signal 102, 110, 111 Trigger signal 103, 105 Positive logic output signal 104 , 106 Negative logic output signal 107, 108 Output signal 109 Trigger enable signal

Claims (1)

[Claims] 1. A trigger circuit for generating a trigger signal of an oscilloscope, comprising: a first comparator to which an input signal and a trigger level signal are input; and a hysteresis circuit to which the input signal and the trigger level signal are input. A second comparator, a logical operation means for calculating the logical sum of the outputs of the first and second comparators, and a holding means for holding the state of the trigger enable signal based on the output timing of the logical operation means. A trigger circuit characterized by being provided.