JP2666429B2 - Differentiator circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a differentiating circuit in a digital circuit.

[Conventional technology]

2. Description of the Related Art Conventionally, this type of differentiating circuit, especially when it is formed inside an integrated circuit or a gate array or the like, as shown in FIG. As a result, a differential waveform was obtained. In FIG. 2 (a), such a conventional general differentiating circuit includes inverters 2, 3, 4, 5, 6 connected in five stages between an input terminal 7 and an output terminal 8, and an AND circuit. 1 and is configured. FIG. 2 (b) is FIG. 2 (a)
3 is an operation waveform diagram of FIG.

The input terminal 7 receives a differentiated waveform CIN, the output terminal 8 outputs a differential wave determination COUT, and the output of the inverter 6 outputs a waveform C1.

As can be seen from the timing chart of FIG. 2B, this conventional differentiating circuit uses the inverters 2, 3, 4, 5, and 6 as delay circuits and generates a pulse having a width corresponding to the delay of the delay circuit. , The differentiated waveform COUT is obtained from the differentiated waveform (input waveform) CIN.

[Problems to be solved by the invention]

In the above-described conventional differentiating circuit, the delay circuit, that is, the delay of the inverters 2, 3, 4, 5, and 6 itself is an element that determines the pulse width of the differentiated waveform. In order to secure a required pulse width, the delay must be determined in consideration of the influence of the process variation on the delay. However, since the circuit using the differential waveform and the differentiating circuit are completely independent, if the delay setting is insufficient, an insufficient pulse width is generated for the circuit using the differential waveform, There is a disadvantage that it causes a malfunction.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a differentiating circuit which solves the above-mentioned disadvantages and has a sufficient delay setting so that an accurate differentiated waveform can be always obtained even if there is a variation in the manufacturing process.

[Means for solving the problem]

An output terminal of a data flip-flop having a data input terminal and an input terminal of a differentiated input waveform is directly connected to an inverting reset terminal of the next-stage toggle flip-flop by a connection line, and the clock terminal is connected to the inverting terminal. Connected to a reset terminal via delay means for giving a time difference to an active state, and the clock terminal is used as an output terminal to another flip-flop having characteristics equivalent to those of the toggle flip-flop. An output terminal of the flip-flop is connected to a reset terminal of the data flip-flop by a connection line without passing through another circuit element, and when data supplied to the data input terminal is at a high logic level, The pulse width of the output waveform of the data flip-flop, which becomes active in response to the differentiated input waveform, is Set by directly resetting the data flip-flop at the output of Le flip-flop, and is characterized by maintaining a constant pulse width.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 (a) is a circuit block diagram showing a differentiating circuit according to one embodiment of the present invention, and FIG. 1 (b) is a timing chart of FIG. 1 (a). 1 (a) and 1 (b), the differentiating circuit of the present embodiment includes flip-flops 14, 15, 17, 18
, A delay circuit 16, an input terminal 11, an output terminal 12, a signal input terminal 10, and a Q output terminal 13 of a flip-flop 15.
And a Q output terminal 14 of the flip-flop 14.

Here, the flip-flop 15 is an edge trigger type data flip-flop, the flip-flop 19 is an edge trigger type toggle flip-flop, the flip-flops 17 and 18 are flip-flops using differential waveforms, and the delay circuit 16 is a flip-flop. A delay circuit for securing the reset release time of the loop 19, the waveform CIN is the differentiated input waveform at the input terminal 11, the waveform COUT is the output differential waveform at the output terminal 12,
Waveforms C1 and C2 are the Q output waveforms of flip-flops 15 and 19, input D is the data input, input C is the clock input,
R, indicates a reset input, and output Q indicates a non-inverted output.

Next, the operation will be described. In the edge trigger type data flip-flop 15, the clock is activated by the rise of the differentiated waveform CIN, the value "1" set in the data is output to the output, and the rising 20 of the waveform C1 is obtained. Next, the inverted reset input of the flip-flop 19 is released by the waveform C1, and the clock is ready to be accepted. Next, the waveform C1 passes through the delay circuit 16 for securing the reset release time of the flip-flop 19,
The rising edge of COUT 21 is obtained, and this is used as an active clock to the flip-flop 19. With this clock, the output C2 of the flip-flop is inverted, and a rising 22 is obtained. By the rising edge 22 of the waveform C2, the flip-flop 15 is reset, the falling edge 23 of the waveform C1 returns to the “0” level, the flip-flop 19 is reset, and the falling edge 25 of the waveform C2 returns to “0”. At the same time, the rising edge 24 of the waveform COUT returns to the “0” level,
A differential waveform is obtained at COUT. The circuit using the waveform COUT is a flip-flop having the same performance as that of the normal flip-flop 19, so that if the flip-flop 19 operates, the circuit operates reliably.

That is, the differentiating circuit according to the present embodiment has a feature that it is determined by feedback from a circuit that uses the pulse width of the differential waveform.

〔The invention's effect〕

As described above, the present invention feeds back the differential waveform to be used to the differentiating circuit itself, so that when this differential waveform is used as a clock, there is an effect that a reliable pulse width for operating the using circuit can be obtained. .

[Brief description of the drawings]

FIG. 1 (a) is a circuit block diagram of a differentiating circuit according to one embodiment of the present invention, FIG. 1 (b) is a timing chart of FIG. 1 (a),
FIG. 2A is a circuit block diagram of a conventional differentiating circuit, and FIG.
FIG. 2B is a timing chart of FIG. 2A. 15: Edge-trigger type data flip-flop, 19: Edge-trigger type toggle flip-flop, 17, 18: flip-flop. 16 Delay circuit, 2, 3, 4, 5, 6 Inverter, 1 AND gate, CI
N: Differentiated input waveform, COUT: Differential output waveform, C1, C2 ...
… Waveform of each node, 7,8,10,11,12 …… Terminal, 13,14 ……
Q output terminal, 20, 21, 22 ... rising, 23, 24, 25 ... falling.

Claims (1)

(57) [Claims] An output terminal of a data flip-flop having a data input terminal and an input terminal of a differentiated input waveform is directly connected to an inverting reset terminal of a next-stage toggle flip-flop by a connection line. The terminal is connected to the inverting reset terminal via delay means for giving a time difference to an active state, and the clock terminal is connected to an output terminal to another flip-flop having characteristics equivalent to those of the toggle flip-flop. The output terminal of the toggle flip-flop is connected to the reset terminal of the data flip-flop by a connection line without passing through another circuit element, and the data supplied to the data input terminal is at a logic high level. A pulse of the output waveform of the data flip-flop which becomes active in response to the differentiated input waveform when the signal is at the level It is set by directly resetting the data flip-flop at the output of the toggle flip-flop. A differentiating circuit characterized by maintaining a constant pulse width.