JPH0119300B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a frequency comparator suitable for use when converting a digitized system into an LSI, and realizes a frequency comparator that operates stably with a relatively simple configuration. It is intended for this purpose.

The most typical example of this type of frequency comparator is shown in FIG. 2 of US Pat. No. 3,069,623, which is shown in FIG.

When the pulse train shown by the solid lines in FIG. 2 A' and B' is applied to input terminal A and input terminal B of the circuit in FIG. 1, NOR gates 1 and 2, AND gate 3,
4. The output signal waveforms of the NOR gates 5 and 6 are as shown in FIG. When there are two or more leading edges of the pulse signal applied to the input terminal B between one leading edge and the next leading edge, the AND gate 4 generates an output signal (4a in FIG. 2), The output level of the NOR gate 6 is set to "L", and as a result, the output level of the NOR gate 5 shifts to "H". When there are two or more leading edges of the pulse signal applied to the input terminal A before the leading edge, the
AND gate 3 generates an output signal (Fig.
a) The output level of the NOR gate 5 is set to "L", and as a result, the output level of the NOR gate 6 is shifted to "H".

Therefore, depending on the output state of the bistable circuit in which the input terminals and output terminals of the NOR gate 5 and the NOR gate 6 are cross-coupled with each other, the input terminal A and the input terminal B are It is possible to compare the frequencies of the applied pulse signals.

That is, if the frequency of the pulse signal applied to the input terminal B becomes higher than the frequency of the pulse signal applied to the input terminal A, the output level of the NOR gate 5 becomes "H"; When the frequency of the pulse signal applied to the input terminal B becomes lower than the frequency of the pulse signal applied to the input terminal A, the output level of the NOR gate 6 becomes "H".

In other words, the frequency comparator shown in FIG.
A set composed of NOR gates 2. Reset. All of the pulse signals become valid pulses for the flip-flop, and the set... Reset. A flip-flop repeats the inversion operation, but when the frequency of the pulse signal applied to one input line becomes higher than that of the other, that is, from the leading edge of the pulse signal applied to the other input line to the next leading edge. The leading edge of the pulse signal applied to one input line during
When there are more than one pulse signal, the second and subsequent pulse signals are set by the NOR gate 1 and the NOR gate 2. Reset. Since this is an invalid pulse that cannot invert the output state of the flip-flop, the AND gate 3 is
Alternatively, the levels of the input terminals of the AND gate 4 both become "H" and an output signal is generated, thereby causing the second set. Reset. The output state of the flip-flop is determined.

By the way, the above-mentioned operation is performed only when the pulse width of the pulse signal applied to the input terminals A and B is extremely short, but if it is too short, each gate will not be able to fully respond.

To explain this pattern using Figure 2, the output levels of NOR gates 1 and 6 are “H” in advance.
When a pulse signal is applied to input terminal A while the output level of NOR gates 2 and 5 is "L", the above
The level of one input terminal of NOR gate 1 is “H”
Therefore, the output level of the NOR gate 2 becomes "L" with a delay of one gate's worth of signal transmission time, and the output level of the NOR gate 2 becomes "H" with a further delay of one gate.

By the time the output level of the NOR gate 2 shifts to "H", the pulse at the input terminal A has disappeared. That is, if the trailing edge of the pulse signal applied to the input terminal A has passed, then
Although the output level of the AND gate 3 never becomes "H", as shown by the broken line in FIG. 2A', when the output level of the NOR gate 2 shifts to "H", the input terminal A If the level remains at "H", the output level of the AND gate 3 becomes "H" with a delay of one gate. (Figure 2 3
b) At this point, the output level of the NOR gate 5 has already become "L", so the output state of the flip-flop formed by the NOR gate 5 and NOR gate 6 will not be inverted; A pulse signal is applied to the NOR gate 1.
When the output level returns to “H” again, Fig. 2
As shown by the broken line B' (Bb in Figure 2), if the level of the input terminal B remains "H",
After a delay of one gate, the output level of the AND gate 4 becomes "H" (FIG. 2, 4b), and the output level of the AND gate 4 becomes "H" (FIG. 2, 4b).
When the output level of NOR gate 6 becomes "H", the output level of NOR gate 6 becomes "L" with a delay of one gate as shown in FIG. It becomes H”.

Thereafter, each time a valid pulse is applied to the input terminals A and B, the NOR gate 5 and the NOR gate 6 perform the set. Reset. Since the flip-flop repeats the inversion operation, it becomes impossible to compare the frequency level of the input pulse signal based on the output state of the flip-flop by the NOR gate 5 and the NOR gate 6.

As can be seen from the above explanation, in order for the circuit shown in Fig. 1 to operate normally, that is, to operate as a frequency comparator, the pulse width of the pulse signal applied to input terminals A and B (from the leading edge to It is necessary to make the width (to the trailing edge) narrower than the width equivalent to the delay time of two gates.

In the embodiment described in the above-mentioned US Pat. No. 3,069,623, the pulse signals shown in FIG. 2 A' and B are created by a differentiating circuit, but a general differentiating circuit (for example, a differentiating circuit using a capacitor and a resistor) is used. Therefore, it is difficult to obtain a pulse width shorter than the width equivalent to the delay time of two gates, and if it is too short, problems arise such as not being able to drive each gate sufficiently. In particular, when converting a system into an LSI, it is difficult to make fine adjustments to individual circuit parts, so it is not reliable to use the circuit shown in Figure 1, which causes malfunctions if the pulse width of the input signal becomes even slightly wider. It is also undesirable from a sexual point of view.

The frequency comparator of the present invention solves the above problems.

FIG. 3 shows a logic circuit diagram of a frequency comparator in an embodiment of the present invention, in which the first input terminal A is
A set consisting of a NAND gate 12 and a NAND gate 13 connected in a cross-coupled manner. Reset. Set terminal 14a of flip-flop 14
and its output terminal 16C is connected to D.
The input terminal 16a of the NAND gate 16 is connected to the clock terminal _C1 of the flip-flop 15, and the second input terminal B is connected to the reset terminal 14b of the flip-flop 14. terminal
D ₂ is the output terminal 14 of the flip-flop 14
It is connected to the clock terminal C2 of the D flip-flop 18, which is connected to the clock terminal _C2 .

Further, the inverting output terminal 14d of the flip-flop 14 is connected to the delay terminal _D1 of the D flip-flop 15, and the output terminal 15C of the D flip-flop 15 is connected to the NAND gate 16.
The inverting output terminal 18d of the D flip-flop 18 is connected to the set terminal _S1 of the D flip-flop 15.

Now, FIG. 4 is a signal waveform diagram of each part to explain the operation of the digital frequency comparator shown in FIG.
3', 17', 18', 18d', 16', 15' are
respectively, a second input terminal B, a first input terminal A, an inverter 11, a NAND gate 12,
The signal waveforms appearing at the output terminal 18C of the NAND gate 13, the inverter 17, the D flip-flop 18, the inverted output terminal 18d, the NAND gate 16, and the output terminal 15C of the D flip-flop 15 are shown.

Here, assuming that a reference pulse of a constant frequency for comparison continues to be applied to the second input terminal B, at time t= _t1 , the first input terminal A
There is no pulse signal coming and the level is “L”
flip-flop 14 is held at the second
Since the output level of the NAND gate 12 continues to be reset by the reference pulse applied to the input terminal B of the NAND gate 12, the output level of the NAND gate 12 continues to maintain "L", and the output level of the NAND gate 13 continues to maintain "H".

In this state, the D flip-flop 18 changes the leading edge (in this case, from "H" to "L") of the reference pulse applied to the second input terminal B.
is triggered every time there is a transition to
Since the level of _D2 maintains "L", its inverted output 18d' does not change from "H", the D flip-flop 15 continues to be set, and the level of output terminal C maintains "H". '.

At time t= _t2 , the flip-flop 14 is set at the leading edge of the pulse signal applied to the first input terminal A, and the output level of the NAND gate 12 shifts to "H".
The output level of gate 13 shifts to "L",
The output level of the NAND gate 16 also shifts to "H", but since the inverted output of the D flip-flop 18 remains "H" and does not change, the level of the output terminal C remains "H".

At time t= _t3 , the output level of the NAND gate 13 shifts from "L" to "H" at the leading edge of the reference pulse, and at the same time, the D flip-flop 18 is triggered, and its output level changes from "L" to "H". The signal shifts to "H", but no further changes occur.

The level change at input terminal A at time t= _t4 causes the output level of NAND gate 12 to shift from "H" to "L" and also causes the output level of NAND gate 16 to shift to "L".

At time t= _t5 , NAND is applied at the leading edge of the pulse applied to input terminal A.
The output level of gate 12 shifts to "H",
The D flip-flop 15 is triggered via the NAND gate 16, but since the output level of the NAND gate 13, that is, the level of the delay terminal D1 of the D flip-flop ₁₅ is "H",
The output level remains "H" and does not change.

Thereafter, when the leading edge of the pulse signal applied to the B terminal and the leading edge of the pulse signal applied to the A terminal appear alternately, D
The output of the flip-flop 15, that is, the level of the output terminal C remains "H" and does not change, but at time t
= t ₆ , the leading edge of the pulse signal applied to the A terminal is 2 between the leading edge (t ₃ ) of the pulse signal applied to the B terminal and the next leading edge (t ₇ ) of the pulse signal applied to the B terminal. times (t ₅ , t ₆ ), the level of output terminal C is “H”
to “L”.

At the leading edge of the pulse at the A terminal at time t= _t6 , the output level of the NAND gate 16 transitions from "L" to "H" and the D flip-flop 15 is triggered, but the output level of the NAND gate 13 at this point is is at "L", so the output level of the D flip-flop 15 is "L".
The level of the output terminal C also becomes "L".

When the leading edge of the pulse at the B terminal arrives at time t= _t7 , the output level of the NAND gate 13 shifts to "H", and the D flip-flop 18 is also triggered, but the output level of the NAND gate 12 is "H". Therefore, the output level of the D flip-flop 18 does not change.

The arrival of the leading edge of the pulse at the A terminal at time t= _t8 causes the output level of the NAND gate 12 to shift to "H", but no further change occurs.

At this point, the pulse applied to the A terminal disappears,
Alternatively, if the frequency becomes lower than the frequency of the reference pulse applied to the B terminal and the leading edge of the pulse at the B terminal appears consecutively before the next leading edge of the pulse at the A terminal arrives, then the output terminal C The level returns to "H" again.

That is, after the leading edge of the pulse at the A terminal appears at time t= _t8 , the time t=
When the leading edge of the pulse at the B terminal appears successively at _t9 and t= _t10 , the delay terminal _D2
D flip-flop 1 when the level of
8 is triggered, its output level shifts to "L", and the inverted output ₂ causes the output of D flip-flop 15 to shift to "H".

After that, even if the leading edge of the pulse applied to the A terminal and the leading edge of the pulse applied to the B terminal appear alternately at t ₁₁ , t ₁₂ , t ₁₃ , _{t 14 ,} t ₁₅ , t _{16 ,} t 17 , As long as the frequency of the pulse at the A terminal does not become higher than the frequency of the pulse at the B terminal, the level of the output terminal C remains "H", but at time t=
As shown in _t18 , when the frequency of the pulse at the A terminal becomes higher than the frequency of the pulse at the B terminal and its leading edge appears continuously, the output terminal C is output.
The output level shifts to "L".

Therefore, the circuit of FIG.
When the frequency of the pulse signal applied to the second input terminal B becomes higher than the frequency of the pulse signal applied to the second input terminal B, an "L" output is generated, and the pulse signal applied to the first input terminal A When the frequency of the pulse signal applied to the second input terminal B becomes lower than the frequency of the pulse signal applied to the second input terminal B, in other words, the frequency of the pulse signal applied to the second input terminal B becomes lower than the frequency of the pulse signal applied to the first input terminal A. When the frequency of the pulse signal becomes higher than the frequency of the pulse signal, an "H" output is generated. Moreover,
As is clearer from the signal waveform diagram of FIG. 4, the signals applied to the input terminals A and B do not need to be differential pulses with limited pulse widths as in the circuit of FIG. 1.

Note that the NAND gate 16 in FIG. 3 may be any other logic gate. For example, when using an OR gate, one input terminal of the OR gate is directly connected to the input terminal A without going through the inverter 11, and the other input terminal is connected directly to the input terminal A without going through the inverter 11. The terminal may be connected to the inverting output terminal of the D flip-flop 15.

In addition, in the explanation of the embodiment shown in FIG. 3, the state where the output is "H" is called the set state, and the state where the output is "L" is called the reset state.
In other words, negative logic also holds true, and there is no problem even if the state where the output is "L" is the set state and the state where the output is "H" is the reset state.

As shown above, in the frequency comparator of the present invention, the first input terminal A, the second input terminal B, the first logic gate (NAND gate 12), and the second logic gate (NAND gate 13) ) are cross-coupled and configured, and when pulse signals are applied alternately to the first and second input terminals, the bistable circuit 14 repeats inversion of the output state in response to the arrival of the pulse signal; The output of the bistable circuit is supplied to a delay terminal, and the pulse signal applied to the first input terminal is supplied to a clock terminal, and the pulse signal applied to the first input terminal is capable of inverting the output state of the bistable circuit. a first D flip-flop 15 which is reset when an invalid pulse is applied; one input terminal is supplied with the output of said first D flip-flop; the other input terminal is supplied with the output of said first D flip-flop 15; A third logic gate (NAND gate 16) whose output terminal is connected to the clock terminal of the first D flip-flop, and the output of the bistable circuit is supplied to the delay terminal of the third logic gate (NAND gate 16). A pulse signal applied to the second input terminal is applied to a clock terminal, the output of which is connected to the set terminal of the first D flip-flop, and the pulse signal applied to the second input terminal inverts the output state of the bistable circuit. a second flip-flop 18 for setting said first D flip-flop when an invalid invalid pulse is applied;
and an output terminal C to which the output of the first flip-flop is applied, a stable frequency comparison output can be obtained regardless of the pulse width of the input pulse signal, and therefore the system can be integrated into an LSI. This has great effects, such as eliminating the problem of variations in signal transmission time between individual elements.

[Brief explanation of drawings]

Fig. 1 is a logic circuit diagram of a conventional frequency comparator, Fig. 2 is a signal waveform diagram of each part of Fig. 1, Fig. 3 is a logic circuit diagram of a frequency comparator in an embodiment of the present invention, and Fig. 4 3 is a signal waveform diagram of each part in FIG. 3. 14... Bistable circuit, 15... First D flip-flop, 16... Logic gate, 18... Second D flip-flop.

Claims (1)

[Claims] 1 A first input terminal, a second input terminal, a first logic gate, and a second logic gate are cross-coupled, and pulse signals are alternately applied to the first and second input terminals. a bistable circuit whose output state repeats inversion in response to the arrival of the pulse signal when applied; the output of the bistable circuit is supplied to a delay terminal; and the pulse signal applied to the first input terminal is clocked. supplied to the terminal,
a first D flip-flop that is reset when an invalid pulse that cannot invert the output state of the bistable circuit is applied to the first input terminal; and an output of the first D flip-flop to one input terminal. a third logic gate whose other input terminal is supplied with the pulse signal applied to the first input terminal, and whose output terminal is connected to the clock terminal of the first D flip-flop; The output of the bistable circuit is supplied and the second
A pulse signal applied to the input terminal of the bistable circuit is applied to the clock terminal, the output of which is connected to the set terminal of the first D flip-flop, and the pulse signal applied to the second input terminal of the bistable circuit is capable of inverting the output state of the bistable circuit. a second flip-flop that sets the first D flip-flop when an invalid pulse is applied; and an output terminal to which the output of the first flip-flop is applied.