JPS6361821B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal separation circuit suitable for digital signal processing such as PCM communication and computer processing.

As is well known, for example, when dealing with a serial data signal in which a data signal and a synchronization signal are combined in series, it is often necessary to separate the data signal and the synchronization signal.

An object of the present invention is to provide a signal separation circuit capable of separating a synchronization signal and a data signal from a serial data signal consisting of a data signal and a synchronization signal, respectively, with a simple configuration.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 11 is a signal separation circuit;
12a and 12b are input terminals, and 12c and 12d are output terminals. The input terminal 12a has first and second input terminals.
is connected to one input terminal of each of AND circuits 13 and 14. Further, the input terminal 12b is connected to the output terminal of the AND circuit 13 and the OR circuit 15.
The input terminal of this OR circuit 15 is connected to the other input terminal of the AND circuit 13. The output terminal of this AND circuit 13 is connected to the other input terminal of the AND circuit 14 via an inverter circuit 16. The output terminal of the AND circuit 14 is connected to the output terminal 12c, and the output terminal of the AND circuit 13 is connected to the output terminal 12d.

In the above configuration, the operation will be explained. This circuit receives a serial data signal, for example, a serial arrangement of a data signal and a synchronization signal, which is input to an input terminal 12a, and outputs both of the signals to an output terminal, depending on the rising timing of a control pulse signal input to an input terminal 12b. 12c and 12d, respectively.

First, as the initial state of this circuit, OR circuit 1
5. The output level of the AND circuit 13 is "0", the output level of the inverter circuit 16 and the AND circuit 1
It is assumed that when the output levels of the output terminals 12c and 12d are respectively "1" and "0", the output levels of the output terminals 12c and 12d are "0". In this state, when a "1" level signal is supplied to the input terminal 12a, the OR circuit 15, the AND circuit 13, the inverter circuit 16, and the output terminal 12d are each held in the above state, and the AND circuit 14 satisfies the input condition. Therefore, the output terminal 12c is inverted to the "1" level. If the input conditions remain as they are, the state of the output terminal 12c is maintained until the input terminal 12a reaches the "0" level. Next, in this state, when a "1" level signal is supplied to the input terminal 12b, the output states of the OR circuit 15, the AND circuit 13, the inverter circuit 16, and the AND circuit 14 are inverted, respectively, and the output terminals 12c, 1
The output levels of 2d are inverted to "0" and "1", respectively. Here, if the signal supplied to the input terminal 12b is a continuous step signal, then this circuit is Z=X. output level). The feature of this circuit is the input terminal 12.
The purpose is to perform the same operation as described above even when a pulse signal is supplied to b. That is, input terminal 1
When a "1" level pulse signal is supplied to 2b, at this point, the output terminal 12 is
c and 12d are at "0" and "1" levels, respectively. Here, since the output signal of the AND circuit 13 is fed back to the OR circuit 15, even if the input level of the input terminal 12b becomes "0", the output level of the OR circuit 15 and the AND circuit 13 remains "1". Retained. This state is maintained until the input terminal 12a reaches the "0" level. Therefore,
As a result, the signal supplied to the input terminal 12a is divided and outputted to the output terminals 12c and 12d depending on the rising timing of the pulse signal supplied to the input terminal 12b.

If the above circuit is used, for example _, a serial data signal including a data signal I _D as shown in FIG. It is possible to separate the two as shown in the figure. The data signal I _D shown in Figure 2a
One data has a length equivalent to one repetition period of the synchronization signal I _C , but one data has a length of at least one repetition period of the synchronization signal I C
It is sufficient if the length of the repetition period is sufficient. Also, Figure 2b
The clock pulse signal shown in FIG. 1 has the same repetition period as the synchronizing signal I _C and is a signal whose level is inverted from that of the synchronizing signal. When the signals shown in FIG. 2a and b are respectively supplied to the input terminals 12a and 12b in FIG. 1, the output level of the AND circuit 13 becomes "1" during the "1" level period of the data signal _ID , and " During the 0'' level period, the output level becomes 0 and the data signal I _D is output from the output terminal 12d. Also,
At this time, the input level of the AND circuit 14 is such that when the data signal I _D is at the "1" level, the output level of the inverter circuit 16 is "0", and when the data signal I _D is at the "0" level, the output level of the inverter circuit 16 is "0". Since the value becomes "1", the input condition is not satisfied in either case. Therefore, the output terminal 12c remains at the "0" level.

On the other hand, during the period of the synchronization signal I _C , the output level of the AND circuit 13 is always “0”, so the output terminal 1
2d is always at the "0" level. Further, since the other input terminal of the AND circuit 14 is always kept at the "1" level via the inverter circuit 16, the gate of the AND circuit 14 is controlled in accordance with the synchronizing signal _I.sub.C. Therefore, the synchronization signal I _C is output to the output terminal 12c.

According to the above configuration, the output terminals 12c, It is possible to divide and output into 12d. Therefore, unlike the conventional circuit, a circuit having a memory function is not required, so that the circuit configuration can be simplified.

Furthermore, when the input terminal 12a is at the "1" level, once a pulse signal is supplied to the input terminal 12b, the state will not be reversed by subsequent pulse signals, so it has the advantage of not being affected by chattering, for example. ing.

Next, a gate control circuit using the above signal separation circuit will be explained using FIG. 3. Furthermore, the third
In the figure, the same parts as in FIG. 1 are given the same reference numerals.

FIG. 3 shows an example in which the signal separation circuit 11 shown in FIG. 1 is used to control the opening and closing of the gate.

That is, FIG. 3 shows a configuration in which a timing generation circuit 31 is added to the signal separation circuit 11 having the configuration shown in FIG. The timing generation circuit 31 has a built-in counter and a pulse generation circuit such as a flip-flop, and counts the clock signal CL when the signal supplied to the input terminal 12a rises from the "0" level to the "1" level. is started by a counter, and when the count value reaches a predetermined value, a pulse signal is output from the pulse generation circuit and supplied to the input terminal 12b.

In such a configuration, considering a state in which the signal supplied to the input terminal 12a rises from the "0" level to the "1" level, the count number of the clock signal CL reaches a predetermined value at the input terminal 12b. Since no pulse signal is supplied until then, the input to the input terminal 12b remains at the "0" level. At this time, the OR circuit 15, the AND circuit 13, the inverter circuit 16, and the AND circuit 1 in the signal separation circuit 11
Each output level of 4 is “0”, “0”, “1”,
Since it becomes “1”, the output of output terminal 12c is also “1”.
On the other hand, the output of the output terminal 12d remains at the "0" level. clock signal
When the count number of CL reaches a predetermined value, the input terminal 12
When a pulse signal (“1” level) is supplied to b,
Since the output levels of the OR circuit 15, the AND circuit 13, the inverter circuit 16, and the AND circuit 14 are "1", "1", "0", and "0", respectively, the output of the output terminal 12c is at the "0" level. Therefore, output terminal 1
The output of 2d becomes "1" level. That is, the output of the output terminal 12c is "1" during the period from when the step signal (from "0" to "1") is applied to the input terminal 12a until the pulse signal from the timing generation circuit 31 is applied to the input terminal 12b. level. Therefore, if the count number of the clock signal CL is controlled to control the generation timing of the pulse signal supplied to the input terminal 12b, the output terminal 12c can be controlled.
It is possible to control the period during which the output of the circuit is at the "1" level, that is, to control the gate width or pulse width. Moreover, the output of the output terminal 12d is
The rising edge of the pulse signal supplied to the input terminal 12b brings it to the "1" level, so the input terminal 1
This can be used for gate delay control such as opening the gate after a predetermined time has elapsed since the "1" signal is supplied to 2a. In this case, the delay time can also be controlled by controlling the generation timing of the pulse signal supplied to the input terminal 12b.

As described in detail above, according to the present invention, it is possible to provide a signal separation circuit capable of separating a synchronization signal and a data signal from a serial data signal consisting of a data signal, a synchronization signal, etc., with a simple configuration.

[Brief explanation of drawings]

1 is a circuit configuration diagram showing an embodiment of a signal separation circuit according to the present invention, FIGS. 2a to 2d are diagrams shown for explaining an example of signal separation operation using the circuit of FIG. FIG. 3 is a configuration diagram showing an application example of the signal separation circuit shown in FIG. 1. 13, 14...AND circuit, 15...OR circuit.

Claims (1)

[Claims] A serial data signal consisting of a series arrangement of a synchronization signal with a predetermined repetition period and a data signal whose length is longer than one repetition period of the synchronization signal is supplied to one input terminal, and the synchronization signal and the data signal are connected in series. a first AND circuit that separates and outputs one of the signals; a pulse signal that has the same repetition period as the synchronization signal and whose level is inverted; and a pulse signal that separates and controls the serial data signal; and an output signal of the first AND circuit; an OR circuit to which an output signal is supplied to the other input terminal of the first AND circuit;
and a second AND circuit to which the output signal of the AND circuit is supplied with its polarity inverted and the serial data signal is supplied, and which separates and outputs the other of the serial data signals. Signal separation circuit.