JPS58223924A - Up-down counter - Google Patents

Abstract

PURPOSE:To prevent malfunction, by generating a clock pulse with a high frequency signal and switching up-down information after latching an up-down signal. CONSTITUTION:Q and Q' outputs of a T-FF and an output of latch means 21, 22 are inputted to an NAND gate, an output pair of the NAND gate is inputted to an AND gate, the output of which is inputted to the T-FF at the post-stage. An output of the FF operated with a clock 13 formed from the product between the Q output of a T-FF21 and a Q' output of a T-FF22 with an AND gate 38 or its gate processing output is inputted to the latch means 21, 22 and the T-FF reset with up-down pulses 31, 32. As a result, since the timing for latching the up-down information is shifted surely from the timing for the count operation with the clock, the malfunction is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to counters, and more particularly to an up-down counter that eliminates malfunctions when information is switched between up and down.

A specific example of the prior art is shown in FIG. In Figure 1, 1 to 3 are T-7 lip-flops (hereinafter abbreviated as 7-FF).
, 4-7 are Nante gates, 8°9 is and gates, 10
is an inverter. Further, 11 to 18 are voltage signals. 2 and 3 are time charts of voltage signals 15 to 18 in FIG. 1. Below, we will discuss the specific example in Figure 1.
This will be explained using the time charts shown in FIGS. First, when the signal 11 is high, the inverter 10 causes the signal 12 to be low. Therefore, the outputs of the Nant gates 5 and 7 are both high, and the time chart of each part's signals is as shown in FIG. That is, the signal obtained by inverting the Q output of T-FF 1.2 by the Nantes gates 4 and 6 is sent to the T-input 15 of the next stage.
．． 17, and since the Q of each T-FF is reversed from the previous state at the rising edge of the T input, such a time chart is obtained.

Here, the Q output of T-FF1, 2.5 has a halo of 1. If the row is 0, from the left 000, 100.010, 110
,001,101... and so on. Next, when signal 11 is low, inverter 10 causes signal 12 to be high. At this time, Nantes Gate 4,
Both outputs of 6 become high, and the Q output of the T-FF is inverted by the Nant gates 5 and 7 to become the T input of the primary stage, and a time chart as shown in FIG. 3 appears. Here, the Q output of 7 FF1.2m5 is -(Oe
Oe O) 111 e 011 e 101.00
1. Count down like this.

The drawback of the counter in Figure 1 is that it is in the middle of counting.

(・A”t 7”, I”7.0□, 8, 4
ゎ9-1.

It is to create. This will be explained using FIG. 4.

First, consider the case where the signal 11 is high and becomes low at time 20 of up count 91. The problem is.

Immediately before time 20, signals 14 and 15 and signals 16 and 17
It has the opposite polarity and performs up-counting operation.

After time 20 signals 14 and 15 and signals 16 and 17
This leads to a down-count operation with the same polarity. The result is T
-Q output of FF1, 2, 5 is...101°01
After counting up to 1, after point 20, 01Q, 10
Count down to o, ooo.

A malfunction occurs in which the value changes from 011 to 010 between these two operations. Therefore, in order to prevent this malfunction, a configuration as shown in FIG. 5 is adopted.

The operation of FIG. 5 will be explained below using FIG. 6. In FIG. 6, the signal 19 is a signal that goes low before the up/down signal 11 switches and goes high at the next rising edge of the clock pulse 13. This signal prevents the output of the AND gate 8.9 from changing from low to high when the up/down signals are switched, thereby preventing malfunctions at the time of switching as described above. In the example shown in FIG. 5, first, when the signal 19 falls, the outputs of the AND gates 8 and 9 both become low. After that, due to the rise of the fire clock, the Q output of T-FF1 is 14.
changes from low to high, but since the signal 11 is low, the output of the Nant gate 4 is high. Also T, -FF
The output of the gate 1 changes from high to low, and the output of the Nant gate 5 changes from low to high. Furthermore, since the signal 19 changes from low to high, the signal 15 eventually changes from low to high. In response to this, the Q output of the T-FF 2 changes from high to low, and at this time the output of the Nant gate 6 is high.

The σ output of the T-FF changes from low to high, and since the signal 12 is high at that time, the output of the Nant gate 7 becomes low. If you wait for this and change signal 19 from low to high,
Since the signal 17 remains low, the Q output 18 of the next stage T-FF 5 does not change.

Therefore, the Q output of y F F I + 213 is 001.101 to 011. while signal 11 is high. and changes in the up direction, and after the change of signal 11, gll.

It changes downward to 1o1.001, and there is no error count during this period.

The above method can prevent error counting.

There is a drawback that a complicated mechanism such as control by a microcomputer or the like is required to generate the signal 19 required for this purpose.

The purpose of the present invention is to have a simple configuration and no malfunction.
The purpose is to provide an up-down counter.

The main focus of the present invention is that after latching the up and down signals,
It is possible to generate a clock pulse using a high frequency signal, or to switch up and down information by detecting that the clock has spread to all stages of the counter.

An embodiment of the present invention will be described below with reference to FIGS. 7 and 8. In the figures, 1 to 18 are the same elements as the numbers in the previous figures. Also, 21 to 25 are T-FF, 2a is R5-FF, 25
．． 26 is Nantes Gate, 2 Hamaor Gate, 28, 2
9 is an inverter, and 60 is a voltage signal. 31, 52
is a pulse with a certain pulse width along with up and down, and 30 is up.

The clock is sufficiently fast compared to the down switching time.

First, in this system, the signal 37 is the row T-FF1.2.
It is assumed that the ζ outputs of 3 are each 01rJ. In the state of waiting for up and down signals 51 and 32, T-FF2
If either of the ζ outputs 1 and 22 is low, the output of the Nant gate 35 becomes high, and the clock 3o is inverted by the Nant gate 26 and input to T-FF21L/c, and in Luno, 35.36 is always high. be. Therefore, T
-FF2s is reset, its ζ output is low, (No. 1 13 is high, the outputs of Nant gates 4 and 5 are both high, the output of inverter 28 is low, the output of Nant gate 6.7 is high, signal 17 is high, It is in a high state.As shown in Figure 8, Tic, R5-FF2dVC high pulse signal 31 is j
When input, the signal 37 goes high, and the OR gate 27 transmits a similar pulse signal to the signal 63, which resets the 7-FF 21.22 to ζ
At the same time as the output becomes low, the reset of the T-FF 25 is released. Next, at the falling edge of signal 61, T 1121m
22 is reset, and the inverter 29 causes T-
Since the rising input is applied to the FF 23, its ζ output changes from low to high.

Then, Nante gate 4p5p6 opens and T on the counter
- A state is reached in which the change in the output of the FF is transmitted to the next stage. T-
The FFs 21 and 22 count until the sum signal 33 of the signals 51 and 32 goes low, the reset is released and the 3005th clock is input, and when the ζ output 55156 becomes high, the Nant gate 25 stops the counting operation. , return to the initial state. During this operation, when the ζ output is inverted to high by the second clock 3o, the T-FF 2s is set and the ζ output becomes low, and the Nant gate 15 triggers the rise of 7pp1. Inputs 15 and 17 of T-FF2.5 of the counter are:
ll',, when counting, that is, 57 is high and the previous stage ζ
When the output is high, the signal 15 is low for a period of time, and returns to high as the signal 15 becomes high. This rising edge triggers the T-FF in the next stage.On the other hand, when ffT is low during down-counting, if the ζ output in the previous stage is high, it is transmitted to the T-FF in the next stage. For example, the 8th
In the case of the figure, when signal 14 is high and signal 37 is high.

Signal 15 goes low for the duration of signal 150 low, and otherwise remains high. Also, during the same up-count, if signal 16 is high, signal 17 goes low, and T-
It can be a trigger for FF5. Conversely, when the signal 57 is low and the count is down.

Only when the signal 14 (or 16) is O, the signal 15 (including 17) becomes low and can invert the T-FF 2 (or 3) of the primary stage.

Another embodiment of the present invention will be described below with reference to FIGS. 9 and 10. This example uses only flip-flops 21e and 22 to generate the clock 15, and the basic operation and constituent elements are almost the same as those shown in FIGS. 7 and 8. The added element is an AND gate 38. The amplifier down pulses 31 and 52 reset the flip-flops 21 and 22 with the same force as in the previous example.
However, in this example, it is AND gate! T- by 18
The difference is that the product of the ζ output of the FF 21 and the ζ output of the T-FF 22 is calculated.

Another embodiment of the present invention will be described with reference to FIGS. 11 and 12. In FIG. 11, 40 is a /)-FF, 41 is an AND gate, and 42 is a voltage signal. 7-FF 1 , ζ of 213
Suppose the output is initially 0t1=0.

FIG. 12 shows a time chart when counting is performed. This will be explained in detail. TFFl is signal 1
It is reversed at the rising edge of 5.

Signal 15 is when the ζ output of T-FF40 and the ζ output of T-FF1 are both high, or when the ζ output of T-FF40 and the T-FF
When outputs 1 and 5 are both high, signal 5
It becomes low only during the high period of 3.

Also, the signal 17 is generated when the ζ output of 7-FF40, the ζ output of 7-FF2, and the signal obtained by inverting the signal 15 are high, or when the ζ output of T-FF40, the ζ output of T-FF2, and the signal 15 It becomes low either when the inverted signal is high or in either case. Therefore, the time chart becomes as shown in Figure 12, and the Q output of TF F1 # 2 I s changes from the left to 010°100e010*110*010.

The counting direction changes from town, up, and down. The difference from the previous example is that the AND gate 41 detects when the counter operation is finished, and at that point the T-FF 4o takes in the up and down data.
The down switching is delayed by one input. However, unlike the previous example, it has the advantage of not requiring a clock that is sufficiently faster than the switching of the up and down signals.

According to the present invention, by adding a small number of flip-flops, it is possible to reliably shift the timing of latching up/down information and the timing of counting operation using a clock, which is effective in preventing malfunctions.

[Brief explanation of drawings]

(, 11W-Figure 7't'''r
2.3.4.6 is a diagram showing a timing chart for explaining the operation of the conventional example. FIG. 7 is a block diagram showing an embodiment of the present invention. FIG. 8 is a timing chart diagram for explaining its operation.
Figures 9 and 11 are block diagrams showing other embodiments;
0 and 12 are timing charts for explaining the operation. ' * 2 p 5 * 21p22140...T-F
F4.5.6.7... Nantes Gate 8.9... And Gate 24... R5-FF 27... Or Gate f 2 Day f 3 Fig. 8 years old 4 Figures 5 Figures 6 Father” +8 8 1-11 Figure 18 (tj

Claims (1)

[Claims] 1. Input the Q' and Q outputs of the T-7 lip-flop in the previous stage and the output of the latch means to a Nant gate, input the Nant gate output pair to an AND gate, and input the #AND gate output. It has a configuration that inputs the input to the T-flip-flop at the subsequent stage, and is characterized in that the output of the flip-flop operated by a certain clock or the gate processing output thereof is input to the latch means and the T-flip-flop. up/down counter. 2. a logic gate that transmits the input to the latch means to the T-flip-flop; a second AND gate whose input group is the T-input to the T-flip-flop;
A D-flip-flop is provided whose T input is the output of the AND gate, and whose D input is the output of the latch means.
2. The up/down counter according to claim 1, wherein the output of the flip-flop is input to the Nant gate.