SU1221743A1 - Controlled pulse repetition frequency divider - Google Patents

Abstract

The invention relates to a pulse technique and can be used in computing and automation. The device contains pulse input 1, input 2 controls the mode of operation, with a signal O, the device has a division factor K + 1, and with a signal 1 - K, input 3 controls the division ratio, control input bus, pulse output 8, output 9 of the device, the code on which corresponds to the number of pulses fed to the input 1, output buses 10–13, triggers 14–17 with counting inputs, generates a binary N-bit pulse counter, D-flip-flop 18, elements 19-23 AND –NE, elements 24 AND , pulse keys 31 and 32 with control signal memorization. Introduction to the device of half-adders 27-30, element 25 AND and element 26 OR allows to expand the functionality by using it in counter mode while maintaining the duration of the input pulse on the code of the device. 3 il. i (L § to to H 4 ;; SA

Description

The invention relates to a pulse technique and can be used in computer systems and automation.

The purpose of the invention is to expand the functionality by allowing the device to be used in counter mode while maintaining the duration of the input pulse at the device output, as well as obtaining the division factor K ,, and.

Figure 1 is a circuit diagram of a controlled pulse frequency divider; 2 is a schematic diagram of an impulse key with a control signal memorization. FIG. 3 is a timing diagram of the operation of a pulse key with memorization of a control signal.

The controllable pulse frequency divider (Fig. 1) contains a pulse input 1, onto which a pulse signal is applied, the frequency of which must be divided into a certain number; input 2 controls the mode of operation (with a signal O, the device has a division factor K + 1, and with a signal); input 3 control division factor, bus 4-7 input 3 control. (tire 4 is the younger bus and tire 7 is the oldest bit); pulse output 8 of the device, where the division factors K or K + 1 are realized, where k is the number specified at control input 3; parallel output 9 of the device, the code on which corresponds to (equal to) the number of pulses fed to the input 1; individual tires 10-13 output 9; triggers 14-17 with a counting input, forming a binary N-bit pulse counter (figure 1); D-trigger 18; elements 19-23 AND-NOT, the first 24 and second 25 elements AND, the element 26 of RShI, half-mators 27-30 with outputs of the sum S and transfer C; the first 31 and second 32 pulse keys with control signal memorization.

The switching input C of the first pulse key 31 with the storage of the control signal is the input of the device, the control input V is connected to the output of the first element 24 And whose inputs are connected to the outputs of the corresponding elements 19 and 22. NAND, the first inputs of each

five

one

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5 o

five

five

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connected to the corresponding 4-7 control-input control bus widths 4-7, the first and second outputs of the first pulse key 3 are connected respectively to the counting input and the reset input of the N-bit counter on triggers 14-17, the second output of the first pulse key 31 connected to the switching input of the second pulse key 32, the output of which is the output of the device, the output of element 26 OR is connected to the control input V of the second pulse key 32, the first and second inputs of the (N + 1) -th element 23 AND-NOT are connected respectively to the inversethe output of the trigger 18 and to the control input of the operating mode of the device connected to the D input of the trigger 18 and to the first input of the half accumulator 27 of the first discharge, the transfer output of which is connected to :. To the first input of the second element I 25, the output of which is connected to the first input of the half adder 28 of the second discharge, the transfer output of each half adder 28 and 29 is connected to the first inputs of the half adder 29 and 30 of the older discharge, and the second inverse input and the inverse output of the sum of half adder 27, 28, 29 and 30 of each bit are connected respectively to the inverse output of their bit counter on flip-flops 14-17 and to the second inputs of elements 19-22 AND-NOT of their bit, the trigger output 18 and its inputs C and R are connected respectively to the second entrance of the second element And 25, to the first and second j outputs of the second pulse key 32, the first and second inputs of the element 26 OR are connected respectively to the bus 4 controlling the division of the low-order bit and the output (N + l) -ro of the element 23 AND-NOT.

A signal 1 is generated at the output of the NAND element, however, the state of the device does not change, since the signal O is at the output of the NAND element 21. The next three pulses from input 1 increase the number in the counter on triggers 14-17 to value 4. At the control input V of key 31, the signal O still remains. The fifth pulse applied to input 1 switches to the first output of key 31 again and switches trigger 14 to state 1. The counter on triggers 14-17 now contains the number 5,

3

the signals 1 are set at the outputs of all elements 1-9-22 AND-NOT, the signal 1 is set at the output of element 24 AND and the control output V of key 31, which causes the sixth pulse from input 1 to switch to the second output of key 31 and key 32 passes to exit 8 of the device.

Thus, in the considered mode, the frequency division of the pulses fed to the input 1 by the number K +1 occurs,

In the second mode of operation, when signal 1 is at input 2, the division factor of the device is k. In the initial state, the inverse outputs of the triggers 14-17 have signals 1, the trigger 18 is in the state O, therefore the inverse outputs of the sum of half summers 28-30 have signals 1, and the inverse output S of half summator 27 has a signal O.

When the digital code at input 3 of control is 1 (on bus 4 - 1, and on other buses is O), the inverse output of the sum S of half-adder 27 has a signal O, while the output of element 19 is NOT the signal I, at the outputs of elements 20-22 | AND-NOT - also signals 1, at the output of element 24 AND - signal 1, the pulses from input 1 are switched to the second output of key 31, are fed to the switching input C of key 32 and are switched to output 8, because at the control input V key 32 has a signal), coming from bus 4 via OR element 26. Thus, when the code of the input 3 is equal to 1, the device divides the pulse frequency coming to its input 1 by a value.

27 S - 28 S - 29 S - 30 S - C -, C - C - C - 19 - 20 - 21 - 1, 22 - 1,

signal 1 is generated at the output of element 24I. A fifth pulse from input 1 switches to the second output of key 31, enters the switching input of key 32, and switches to output 8, since the control input V of key 32 has a signal 1 from the output of element 23 AND -NOT and with inverse trigger output 18.

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When the digital code at input 3 of the control is different from O and 1, signal 0 is in the initial state of control V of key 31. Up to 5, we assume that the code of the number at control input 3 is equal to 5 (on buses 4 and 6, signals 1 , on tires 5 and 7 - signals O). In the initial state, the trigger 18 is in the state

10 O, therefore the transfer from the half adder 27 is not passed to the input of the half adder 28. At the inverse outputs of all triggers there are signals 1, at the inverse outputs of the sum S half of the 15 adders 27 are 28 - 30 - 1, at the outputs of the AND-NE elements 19 - 1, 21 - O, 22 - 1, at the output of the element 24 AND is the signal O, which is-. steps into the control input V kly20 cha 31.

The first pulse from input 1 is switched to the first output of key 31 and switches the triggers 14 and 18 to state 1, while on bus 10 25 confirming the fact of recording one pulse to the counter on triggers 14-17J, half summers 28-30 are connected to the transfer output C of half summator 27, while the following states are set at the inverse outputs of the sum of half adders: 27 - 1, 28 - 1, 29 - 1, 30 -, at the outputs of the AND-NE elements 19 - O, 20 - 1, 21 - O, 22 - 1, on you, with the course of the element 24 And the signal O.

The second, third and fourth pulses are also switched to the first output of the key 31. These pulses bring the number in the counter on triggers 14-17 to 4 to 4, and the device enters the following state (at the inputs of half adders and elements):

Thus, the device divides the frequency by the value of K,

A pulse key with a memory of the control signal and used in the proposed device is depicted 55 in FIG. 2, where: 33 is the switching input C of the pulse key with the memory of the control signal; 34 - control input V key; 35 and 36, the first and second keys of the key; .37 -40 elements OR NOT; 41 - inverter.

The device works as follows.

Each pulse key has a switching input C, a control input V and two output signals, the pulses applied to input C are switched at the first output (located at the top) of the key, and at V-1 - at the second output (located at the bottom) of the key.

J In the initial state, all the triggers 14-17 are in; state O; Consider the operation of the device when the operating mode control signal is input 2, and the division factor of the device is K + 1.

With a digital code O at input 3, the output of each element 19-22 AND-NOT has a signal 1, the output of element 24 I is a signal 1, and at the control input V of key 31 is a signal 1. Supplied from input 1 to the switching input C of key 31 the pulses are switched to the second output of the key 31, are fed to the switching input of the pulse key.32 and pass to the output 8 (since the output of element 23 AND-NOT and element 26 OR, if input 2 of signal O is present, has a signal

one).

When the code of the number at input 3 of the control, other than o, the frequency is divided by the number K + 1. Suppose that the code of the number at input 3 of the control is equal to 5 (on buses 4 and 6, signals 1, on buses 5 and 7, signals ABOUT). At input 2 there is a signal about, therefore at the outputs of the sum of 5 all half-adders 27-30 the same signals as at the inverse outputs of the triggers 14-17. In the initial state, these outputs have signals 1, therefore, at the outputs of elements 19 and 21 of AND-NO, there are signals about, and at the output of element 24, the signal about. The first pulse applied to the G input is switched to the first output of the key 31, arrives at the counting input of the trigger 14 and switches it to state 1.

Let us assume that at signal O at input V, the pulse applied to input C always commutes to the first output 35, and at signal 1, the fed in: C input switches to the second output 36,

In the initial state, the input 33 and the output 35 and 36 have the signals O. At the control input V 34 5 we set the signal O, while the output of the element 40 has a signal 1, the output of the element 37 is O, and the output of the inverter 41 - one,

The signal 1 to the input of the commutation of the C 33 leads to the establishment of the signal O at the output of the inverter 41, while at all the inputs of the element 38

there are signals

and on his vyM 1 II

course - signal 1

The change of the control signal during the switching of the signal 1 does not affect the switching due to the presence of feedback from the outputs of the elements 38 and 39 to the inputs of the elements

37 and 40, respectively. The device operates according to the timing diagram of FIG. 3.

From the timing diagram (Fig. 3) of the operation of the pulse key with memorization of the control signal, it is clear that the durations of the pulses at the switching input of the C 33 and the outputs 35 and 36 of the key are always the same, and the change of the control signal at the control input V of the pulse key with memory control does not affect switching.

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The technical advantages of the proposed device in comparison with the device-prototype is the possibility of using the outputs of the meter triggers as bitwise UDF outputs, since the number code on these outputs is always equal to the number

impulses delivered during this cycle of frequency division to the pulse input, as well as the presence of two operating modes with frequency division factors k and K + 1, where K is the number specified by the digital code on the output buses of the division ratio control, which expands the functionality of the proposed devices. In addition, the advantage of the device is the equality of the pulse durations at the input I and the output 8.

Claims (1)

Invention Formula A controlled pulse frequency divider containing an N-bit pulse counter, N AND-N elements, the first AND element, the first and. and the second impulse keys with a memory of the control signal, the switching input C of the first of which is the device input, and the control input Y is connected to the output of the first AND element whose inputs are connected to the outputs of the corresponding IS NOT elements, the first inputs of each of which are connected to the corresponding dividing ratio control buses, and the first and second outputs of the first impulse key with memory of the control signal are connected respectively to the first. - to the counting input, the second one - to the reset input of the N-bit counter and the switching input C of the second impulse key with a memory of the control signal, the output of which is the output of the device, is that in order to extend the functionality by obtaining the division ratio Cd And, a half-adder is inserted into each bit and, in addition, (Vl + l) -I element is NOT entered, the second AND element and the OR element, the output of which is connected to the control input V second pulse key with memorize: na. control signal, the first and. the second inputs (N + I) -ro element AND-NOT connected respectively to the inverse output of the D-flip-flop, to the control input of the device operation mode, the B-input of the S-flip-flop and the first input of the half-accumulator of the first discharge, the transfer output of which is connected to the first input of the second element And whose output is connected to the first input of the half-accumulator of the second discharge yes, with the transfer output of each half-adder, except the first-half half-adder, connected to the first input of the next adder, the second input and output of the sum 5 half-adder of each discharge are connected respectively to to the output of the corresponding N-bit pulse counter and to the second input of the NAND element of the corresponding 0 bit, and the output of the D-flip-flop and its inputs C and R are connected respectively to the second input of the second element And, to the first and second outputs of the first pulse switch c storing the control signal, the first and second inputs of the OR element are connected respectively to the control bus of the division ratio of the first bit and to the output (// + 1) of the 3Q element. AND-NO. J3 phi1.2 jzn Editor M.Petrova Compiled by S. Klevtsov Tehred V. Kadar Order 1620/59 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab.,. 4/5 Branch PPP Patent, Uzhgorod, Proektna St., 4 Sh fi.Z Proofreader A.Zimokosov