SU993260A1 - Logic control device - Google Patents

Description

(54) DEVICE FOR LOGICAL CONTROL

The invention relates to solving devices and can be used to solve logical problems on time Boolean functions in control and automation devices.

A logical device is known that contains a program and logic block consisting of a shift register, AND, | OR elements, a time relay, a command decoder, an input variable inverter 1.. . :;

One device is characterized by a large volume of the program and low speed. .

The closest to the proposed by the technical essence is a logical device containing a software block, a command decoder, input and output elements AND, element OR, element NOT input variable, shift register, element AND, logical unit, time relay, memory element , the element is NOT, the element is And, the trigger. installation of the shift register register

However, when solving a conjunction with n number of variables, it is necessary to have a shift register for n bits and n

And elements connected to the shift register. This causes an increase in the volume of the apprat), which reduces the reliability of the logic device.

The purpose of the invention is to reduce the volume of hardware and increase the reliability of the device.

The goal is achieved by the fact that in the device containing

W serially connected program block consisting of serially connected pulse generator; Sov and memory block, decoder commands, the first and second groups of outputs which are connected respectively to the first inputs of the input elements And group and output elements And group, the second inputs of the output elements and the group and the last input element AND of the group are connected to the output of the logical multiplication block containing the element NOT and the element AND, the second input of the first input element AND of the group is connected via a time relay

25 to the output of the first output element AND of the group, the second input of the input element AND of the group is connected through the memory node to the output of the second output element AND of the group, the second inputs 30 of all subsequent input elements AND

the groups, except for the last, are connected to the inputs of the device variables, the outputs of the input elements AND groups are connected to the inputs of the OR element, the output of which is connected to the first input of the Element NOT of a logical block; | Ngg,; the second input of which is connected to the output of the sign of inversion of the memory block of the program block, the output of the first bit of the address of which is connected to the first input of the first element I and through the NOT element to the first input of the second element I, the second 1 inputs of the first and second elements I connected to the output of the sync pulse generator, the input of which is connected to the output of the pulse generator of the program block, the outputs of the first and second elements And are connected to the corresponding trigger inputs, the single output of the trigger is connected to the input of the shap the pulse pulse, the outputs of the output elements AND groups, except the first and second, are the outputs of the device, the logical multiplication unit contains two counters and a comparison circuit whose output is connected to the output of the block. The logical multiplication, the first and second inputs of the comparison circuit are connected to the outputs of the first and the second counter, respectively, the output of the sync pulse generator is connected to the counting input of the first counter and to the first input of the AND element, the second input of the second is connected to the output of the NOT element, the output of the AND element is connected to the counting At the input of the second counter, -controlled inputs of the first and second counters are connected to the output of the first discharge of the program memory block: the installation inputs of the first and second counters are connected to the output of the pulse former.

The drawing shows a block diagram of the device.

The device contains a program block 1 consisting of a generator of 2 igetuls and a block of 3 memory, a decoder of 4 commands, input elements of AND 5-9 groups, output elements of AND 10-13 groups, an element of OR 14, block 15 of a monthly multiplication, consisting element 16, element 17, counter 18, counter 19, comparison circuit 20, time relay 21, memory node 22, flip-flop 23, pulse shaper 24, synch pulse shaper 25, HE element 26, and elements 27 and 28.

The device works as follows.

The pulse generator 2 of software block 1 controls the operation of block 3, which generates a command consisting of the address of the input and output element AND and the sign of inverting the input variable. Decoder

4 commands converts the code of the selected address into a control signal supplied to the inputs of the corresponding AND elements 5-13. At the same time, the inversion signal of the input variable is supplied to block 15 at the control input of the element 16, the shaper 25 generates a sync pulse. Input variables encoded by the numbers O and are fed to the inputs of the elements And 7 and 8, the enclosing control system or directly from the sensors | pb. Out with input variables to the input of the element And 5, a signal is sent from the output of the time relay 21, to the input of the element 6 from the output of the memory node 22, and to the input of the element 9-13 from the output of the block 15. Signal from the decoder 4 the command opens one of the input elements AND 7 and V., the input is variable through the element OR 14 and the element NOT 16 is fed to the input of the element AND 17. From the output of the former 25, the synchronization pulse is fed to the counting input of the counter 19 and through the element AND 17 controlled by the input variable , to the counting input of the counter 18. The signal from the programmable unit 1 (the first time d code address) to enable writing in the counters 18 and 19, the outputs of which are respectively connected to the input of the comparison circuit 20. Thus, the counter 18 determines the number of input variables, and the counter 19 determines the number of clock cycles generated by the generator 2 pulses, not needed in Jx to control the operation of block 3. Thus, when solving a conjunction consisting of n number of variables, it is necessary to control the block. 3, this is the number and is recorded in counter 19, and in counter 18, the number of changes in dependence on the sign of inverting the input variable is recorded.

Upon completion of the conjunction decision, the command from block 3 opens one of the output elements AND 10-13 and at their outputs by: is the signal of the result of logical multiplication performed by the comparison circuit 20 over the numbers recorded in the counters 18 and 19.

In the manner described above, all the elementary products that make up the function are checked. And if at least one of them is equal to 1, then at the outputs of the output elements 10–13 a signal appears, including an actuator. The signal from block 3, which allows writing to counters 18 and 19, also goes to element 28 and the element 26 to element 27. And to the second inputs of elements 27 and 28 is supplied a clock pulse from the driver, 25, the outputs of elements 27 and 28 connected respectively to the inputs of the Device. About and Set, trigger 23. Thus, 9 times, upon the arrival of a sync pulse, the trigger 23 is set to a state that is determined by the first digit of the address code. Consequently; when solving a conjunction 1dia, trigger 23 is in a single state and when it returns results in zero. The signal from the transient trigger 23 is fed to the shaper of 24 pulses / which the GL forms a pulse ustgshovky. 18 Vi 19 counters on the front 4FONT of the input signal. At the beginning of the calculation of the new conjunction, the formed pulse imposes all the bits of the counters 18 and 19 to the initial (zero) state. Thus, the introduction of new blocks allows decreasing the equipment volume and increasing the reliability of the device operation by reducing the number of bits in the calculation conjunction Formula of Invention A logical control device comprising sequentially connected program block consisting of series-connected. Generator and power unit; the decoder of the comide, the first and second groups of Bins for which are connected to the first inputs of the input elements and the group and the Taodes elements and the group, the second inputs of the output, elements And groups and the input element and the element I, the second input of the first input element I of the group is connected via a time relay to the output of the first output element I of the group, and the second input of the second input element I of the group via a memory node to the output. the second output of the elec tant and the group, the input of all subsequent input elements and the group, except the last, are connected to the inputs of the variables of the device; the outputs of the adjacent elements of the AND groups are connected to the inputs of the OR element whose output is connected to the first input of the NOT element of the logical multiplication unit whose second input is connected to the inverter memory block f of the program block, the output of the first row of which is connected to the first input of the first element And and through NOT - to the first input of the second element and, - the second inputs of the First and second elements AND are connected to the output of the sinus pulse generator / input of which; connected to the output of the pulse generator of the program block, the outputs of the first and second elements I are connected to the corresponding trigger input, the unit output of the 44 igger is connected to the input of the pulse former, the outputs of the output elements and the group, besides the first and second, are the outputs of the device, for example, which, in order to reduce the volume of the equipment and the reliability of the reliability, the logic multiplication unit contains dVa the count and the comparison circuit, the input of which is connected to the output of the logic multiplication unit, the first and the external inputs of the input cp circuit are connected to the outputs of the first and BTOpord counter, respectively, the output of the forma- Its input is connected to the EleisvFa.IB, the output And i is connected to the counting input of the second counter, the control inputs of the first and second estimators are connected to the output of the first bit of the address of the memory block of the forward block, the inputs of the master and the second and second The counters are connected to the pulse shaper. . Sources of information taken into account in the examination 1. The author's certificate of the USSR I 189630, cl. G 06 F 9/06, 1d64. 2. Authors certificate of the USSR 591858, l, G 06 F 9/06, L prototype).

Claims (2)

Claim A device for logical control, containing a series-connected program unit consisting of series-connected. Pulse memory generator; command decoder, the first and second groups of outputs of which are connected respectively to the first inputs of input elements AND groups and output elements AND groups, second inputs of outputs ·. elements of both the group and the last input element of the group are connected to the output of the logical multiplication block. containing the element NOT and the element AND, the second input of the first input element of the group is connected via a timer to the output of the first output element of the group And the second input of the second input element of the group connected via a memory node to the output. the second output element AND groups, the second inputs of all subsequent input elements AND groups, except the last one, are connected to the inputs of the device * variables, the outputs of the input elements and groups are connected to the input25 whose output is an OR element, the keys to the first input of the element are NOT logical multiplication units , * · second input of which is connected to the output of inverting prize naka ¹ ι memory unit program block, an output of first ra! a series of addresses of which are connected to the first input of the first AND element and through the element NOT to the first input of the second And element, the second inputs of the first and second And elements are connected to the output of the synchronizer, whose input; connected to the output of the pulse generator of the program unit, the outputs of the first and 15 second elements AND are connected to the corresponding inputs of the trigger, a single output of the trigger is connected to the input of the pulse shaper, the outputs of the output.elements and groups, except the first and second, are the outputs of the device And especially with the fact that, in order to reduce the volume of equipment and increase reliability, the logical multiplication unit contains two counters and a comparison circuit, the output of which is connected to the output of the logical multiplication unit: the first and second ode comparison circuits | Nia connected to the outputs of the first and second schetchikasootvetstvenno, the output clock generator is connected to the input of the estimated first counter and to a first input of AND, _ a second input of which is connected to the output member. NOT, the output of element and i is connected to the counting input of the second counter, the controlled inputs of the first and second counters are connected to the output of the first bit of the address of the memory block of the program unit, the installation inputs of the first and second counters are connected to the output of the pulse shaper. . Sources of information taken into account during the examination 1. Copyright certificate of the USSR I "189630, cl. G Rev. F 9/06, 1064. 2. USSR author's certificate No. 591858, ZhL. G 06 F 9 / 06.1976 · _. (prototype).