SU1089764A1 - Ring counter - Google Patents

Abstract

The RING ACCOUNT contains: 1 input bus, zero potential bus of l p cascades, each of which contains the first OR element and the information shift block, and each cascade, starting with the fourth, contains the second OR element, each information shift block consists of m bit shift register and M element IlIHi-HE, the outputs of which are connected to the installation inputs to the zero of the corresponding bits of the shift register, the clock inputs of the bits of which are connected to the clock input of the information shift block and the input bus in the information shift block Formations of the direct output of each odd razor; the shift register is connected to the corresponding inputs of the elements of the OR-NOT other odd bits of the shift register, the direct output of each even digit of which is connected to the corresponding inputs of the elements of the IPI-NOT other even digits of the shift register , the first installation input to Zero is connected to the additional inputs of elements IL11-NOT odd bits of the shift register, the second input of the installation to zero is connected to the additional inputs of elements 1SHI-NOT even digits of the shift register, and the formation input of the first bit of which is connected to the information input of the information shift block is connected to the information output of the information shift block of the previous cascade, in which the information output of the information shift block is connected to the direct output of the last bit of the shift register, the information input of the information shift block of the first cascade connected to the zero potential bus, in each stage the output of the first element OR is connected to the first input of the installation D (L zero of the information shift block, the second input of the installation and in which zero in the cascades, starting from the fourth, is connected to the output of the second element of the RII, which means that, in order to increase reliability, an additional element 00 of the ILM is entered into it, and an element is entered into the information shift block of each cascade which is connected to the control of the output of the information shift block, in which the inputs of the element AND-NOT are connected to the inverted outputs of the bits of the shift register, the first input of the installation, to zero is connected to the additional inputs of the elements 1SH11-NO of even bits of the shift register, extra ADDITIONAL input NOR elements Hilti rasr odd rows, except the first, which are connected to the second input of setting to zero shear P1formatsii unit, inputs of the first OR gate of each odd stage are connected to the control outputs kschimn shear blocks infor

Description

The mapping of other odd cascades, the inputs of the first element OR of each even cascade are connected to the control outputs of the information shift blocks of the other even stages, the control outputs of the cascade information shift blocks are connected to the inputs of the additional OR element, the output of which is connected to the unit installation unit of the shift unit information of the first cascade, in which the installation input to the unit is connected to the installation input to the unit of the first digit of the shift register, the inputs of the second element

OR of each even cascade, starting from the fourth, are connected to the control outputs of the shift blocks of the Shifting format of the preceding odd cascades, the inputs of the second element IL11 of each odd cascade, starting from the fifth, are connected to the control outputs of the blocks of information shift of the previous even-numbered bits, the second The inputs for setting the shift blocks of the information of the second and third stages to zero are connected respectively to the control outputs of the information shift blocks of the first and second stages.

- The invention relates to industrial electronics, automation and computer technology and may find application in the implementation of automation equipment and computer technology.

A ring counter is known, which contains an input, an P-discharge ring register and p OR elements, whose outputs are connected to the installation inputs to the zero of the corresponding bits, a direct output of each discharge is connected to the corresponding inputs of the OR elements of all bits, except the next one in the ring. From 1

The disadvantages of the known device is its relative complexity and the possibility of the disappearance of a single unit in the ring.

A ring counter is known that contains an input bus, a zero bus, a potential, an NAND element and n stages, each of which contains the first and second OR elements and the information shift block, each Shformatzin shift block contains an n-bit shift register and IT elements OR - NOT the outputs of which are connected to the installation inputs to zero of the corresponding bits of the shift register, the clock inputs of the bits of which are connected to the clock input of the information shift block and the input bus, in each information shift block the direct output of each odd ra The shift register case is connected to the corresponding inputs of the OR-NOT elements of other odd 1 bits of the shift register, the direct output of each even-numbered bit of which is connected to the corresponding inputs of the OR-NO elements of the other even shift register bits, the first input of the setting to zero is connected to additional inputs I of the elements OR NOT of the odd bits of the shift register, the second input of the setting to zero is connected to the additional inputs of the elements SH1I-NO of the even bits of the shift register, the information input of the first digit of which The information input of the information shift block is connected to the information output of the information shift block of the previous cascade, in which the information output of the information shift block is connected to the direct output of the last bit of the shift register, the information input of the shift block and the first stage ignition is connected to the bullet potential bus, In each stage, the output of the first element OR is connected to the first input, the home of the zero setting of the information shift block, the second input of the zero setting of which is connected to the output

the second element 11PI, the group of inputs of the first element OR of each stage is connected to the direct outputs of the odd bits of the shift register of the information shift block of all other

5 cascades, groups of inputs of the second HJBi element of each cascade are connected to the npHNftiMH outputs of the even bits of the shift register of the information shift block of all other stages, the inputs of the AND-NOT element are connected to the inverse outputs of the bits of the shift register, ha of the shift block of all cascades, the installation input units of the first bit of the shift register of the shift block and the shape of the first cascade with B1 / 1IND of the NAND element. In the known device, correction of information occurs within 5 D1 W clock of the input and voltage G23. The disadvantage of the device is. its relative complexity is associated with a large number of interstage links, which leads to a decrease in reliability. The purpose of the invention is to increase reliability. To achieve this goal, a ring counter containing 1 input bus, zero potential bus and p stages, each of which contains the first OR element and information offset unit, and each stage, starting from the fourth, contains the second element lUHt, shift block information consists of m-bit shift register and m elements of IL-NOT, the outputs of which are connected to the installation inputs to zero of the corresponding bits of the shift register, the tact Bwe inputs of the bits of which are connected to the clock input of the information shift block and from the input section,each block of information shifts the direct output of each odd bit of the shift register connection with the corresponding inputs of the CLP-NO other odd bits of the shift register, the direct output of each even digit of which is connected with the corresponding inputs of the elements of the OR-NOT other even-numbered bits register times shift shift a, 5

The first input of the setting to zero is connected to the additional inputs of the elements of the OR-NOT odd bits of the shift register, the second input of the installation to the FLOOR is connected to the additional input and the elements of the OR-NOT even bits of the shift register, the information input of the first bit of which is connected to the information input of the shift block information, connected to the information output of the shift unit of the information of the pre-cascade, in which the information output

in addition, are connected to the control outputs of the information shift blocks of the previous odd cascades, the inputs of the second OR element of each odd

the cascade, starting from the fifth, is connected to the control inputs of the 1short 11 shift blocks and the previous even bits, the second inputs of setting the zero information blocks of the second and third stages to zero, respectively, are connected to the control outputs of the information shift blocks of the first and second stages. the information shift block is connected with the direct pulse of the last bit of the shift register, the information input of the shift block of the first cascade information is connected to the zero potential, in each stage the output of the first element ILTUI is connected to the first input of the zero shift block and its format, the second input of the the zero of which in cascades, starting from the fourth, is connected to the output of the second element 1SHI, an additional OR element is entered, and an NAND element, the output of which is connected to the control unit, is entered into the information shift block 1-a 5 output of the information shift block, in which the inputs of the AND-NAND are connected to the inverse outputs of the bits of the shift register, the first input of the setting to zero is connected to the additional inputs of the elements of the even-numbered bits of the shift register, additional inputs of the AND-NOT elements of the odd bits , besides the first one, which are connected to the second input of the information shift block zero, the inputs of the first element OR of each odd cascade are connected to the control outputs of the information shift blocks of other odd full cascades, the inputs of the first element the OR of each even cascade is connected to the control outputs of the information shift blocks of other even cascades, the control outputs of the information shift blocks of the cascades are connected to the inputs of the additional OR element, the output of which is connected to the installation input of the first cascade information shift unit in which the input installation unit is connected to the installation input unit. the first bit of the shift register, the inputs of the second element OR of each even cascade, starting with four of FIG. 1 shows a six-ring annular circuit; 2 shows the implementation of one of the information shift blocks. The secondary ring counter contains information blocks 1.1–1.6, input bus 2, zero potential bus 3, additional element 4 1BI, first elements 5.15 .6 OR, second elements 6.1–6.3 OR Information shift block contains bits 7.1–7.6 of the register shift, element 8 AND-NOT, elements 9.1-9.6 HrUI-HE, clock input 10, information input AND, installation input 12 unit, first installation input 13 zero, second installation input 14 in but information output 15 and controlling output 16. In Figure 1, the input gateway 2 is connected to the clock inputs of the blocks 1.1-1.6, the control inputs of which connected to the inputs of an additional element 4 OR, the output of which is connected to the input of the installation in SDS1ITSU of the block I .., the information input of which is connected to W1SHOY 3 of the potential of logic zero, the information inputs of the blocks 1.2-1.6 are connected respectively to the information outputs of blocks 1.1-1.5, the outputs the first elements 5.1-5.6 OR are connected respectively with the first inputs of the installation to zero blocks -5.1-1.6, the outputs of the second elements 6.1-6.3 are connected respectively with the second-1 and the inputs of the installation to zero blocks 1.4-1.6, the second inputs of the installation in .nol blocks 1 .2 and 1 3 soy ineny respectively with. control outputs of the li-1.2 blocks, the first inputs of the first odd and even elements 5.1, 5.3, 5.5, 5.2, 5.4, 5.6 OR are connected respectively to the control outputs of the odd blocks 1.5, 1.1 1.3 and even blocks 1.4,1,6,1.2, the second inputs of the first odd elements 5.1, 5.3, 5.5 1Ш and even elements 5.2, 5.4, 5.6 The IL are connected respectively to the control outputs of the odd blocks 1.3, 1.5, 1.1 and even blocks 1.6, 1.2, 1.4, the inputs of the second element 6.1 OR are connected to the control outputs of the odd blocks l, lj 1.3, the inputs of the second element 6.2 OR are connected to the control outputs of even blocks 1 , 4, 1.2, the inputs of the second element 6.3 OR are connected to the control outputs of odd blocks 1.1, 1.3, 1.5. 2, information inputs of bits 7, 7.6 are connected 11 respectively to information input 11 and direct outputs, bits 7.1–7.5, the direct output of the last bit 7.6 is connected to information output J5, inverse outputs of bits 7, 1-7.6 are connected to the inputs of element 8, AND-NOT, whose rise is connected to control output 16, clock input 10 is connected to clock inputs of bits 7.1–7.6, installation input to the first bit 7,1 of € ; dinen with an input of 12 units in the unit, the outputs of the elements 9,1-9.6 OR-NOT connected respectively to the inputs of the installation zero bits 7.1–7.6, the first inputs of the odd elements 9.1, 9.3, 9.5 are connected to the direct outputs of the odd bits 7.3, 7.5 and 7.1, the second inputs of the odd elements 9.1, 9.3, 9.5 OR are NOT connected to the direct outputs of the odd bits 7.5, 7.1, 7.3, respectively, the first inputs of the even elements 9.2, 9.4, 9.6 OR are NOT connected to the direct outputs of the pairs 7.4, 7.6, 7.2, respectively , the second inputs of even elements 9.2, 9.4, 9.6 Iimi-HE are connected respectively to the directors and outputs of bits 7.6, 7.2, 7.4, the third inputs of elements 9.1-9.6 of the IPI-NOT with the first input 13 of the installation to zero, the fourth inputs of elements 9.2-9.6, OR-NOT connected to the second input 14 of the installation to zero. It is convenient to begin the analysis of the counter operation by examining the block (Figure 2b) If there is block 1 in one of the odd triggers, for example, bit 7.1, the other two odd digits 7.3 and 7.5 1 cannot appear, so as they are, the corresponding logical elements 9.3 and 9.5 OR-NOT are thus kept in the state on the inputs of the installation in the zero state. Similarly, if there is 1 in one of the even triggers, for example, in discharge 7.2 in two Other even bits 7.4 and 7.6 1 cannot also be created, since they, through the corresponding optical elements 9.4 and 9.6 OR are NOT kept in the state O by the inputs of the installation to the zero state. Therefore, in the bits of the register of the block it is possible to have only two at once, and one of them is in the odd bits, and the other in the even ones. Suppose, for example, 7. and 7.4 there is 1, and at the information input 11 of the block at the moment of action of the clock edge, the level O is maintained. In this case, bits 7.1 and 7.4 accept the zero state, because their inputs D are zero signals and single signals from the outputs of bits 7.1 and 7.4, respectively, through .elements 9.5 and 9.2 OR-NB is held in the zero state, bits 7.2 and 7.5 and therefore all bits of the block take on zero, resulting in a zero signal at the output of element 8 AND-NOT and at the control output 16 of the block . If a single signal is applied to the input 13 of the block, then it sets the zero state of all the bits of the block shift register, and if it inputs to the 4, then all bits except the first 7.1. If one or several single signals are present in an odd block in the ring counter {Fig. 1), the control output of this cascade holds a single signal through the corresponding elements and 5.5 OR the first inputs of the installation keep all in zero state the bits of the other two are odd blocks 1.3 and 1.5. Similarly, for Even Blocks, if one or 11 pulses of single signals are present in one even block, for example, I.4, then through the corresponding elements 5 and 5.6 OR the single signal from the control output of the block 1.4 keeps the zero state all two bits 45

The other blocks 1.2 and 1.6.

Thus, as a result of an accidental failure, 1

Constructive features allows to increase the reliability of the proposed device in comparison with the device-prototype. 48 extra 1 in only one odd block and only in one even. At the same time, single signals from the control outputs of the odd groups by the second inputs of the set to zero directly or through the elements 6.1-6.3 OR all bits of these blocks are kept in the zero state, except the first. Let, for example, single signals are present in blocks 1.1 and 1.4. Moreover, I in block 1.4 can only be in the first bit of a block (figure 2 bits 7.1, since all other bits at the second input of the setup are kept at zero in the zero state, while at least in one preceding odd block there are single signals On the front of a clock pulse in an odd block, tl colors 1 and, moreover, only one, and in the even-numbered block 1.4, the first bit of the block is zeroed, since the information input of block 1.4 gives information from block 1.3 output to O. In case I was in the last discharge of block 1.1, then on the front of the output pulse, it will be rewritten in block 1.2. When all the triggers of the group are reset, the control outputs are set to zero signals that cause the zero signal to appear at the output of element 4 OR under the action of which the unit is set to unit f.1, it is set to one state is the first bit (in Figure 2, bit 7.1 /. In any case, a correction occurs on the clock pulse edge — one and only one unit is set in the ring counter no more than 10 mm of the TSHST. Thus, the reduction of a large number of interstage links due to the introduction of a small number of new

V

Claims (1)

A RING COUNTER containing an input bus, a zero potential bus and η cascades, each of which contains a first OR element and an information shift unit, and each stage, starting from the fourth, contains a second OR element, each information shift unit consists of an m bit shift register and M elements OR NOT, the outputs of which are connected to the zero inputs * of the corresponding bits of the shift register, the clock inputs of the bits of which are connected to the clock input of the information shift block and the input bus, in each information shift block and the direct output of each odd discharge. shift register is connected to the corresponding inputs of the elements OR of other odd bits of the shift register, the direct output of each even discharge of which is connected to the corresponding inputs of the elements of OR other NOT even bits of the shift register, the first input of zero connected to additional inputs of elements of OR-NOT odd bits of the shift register, the second input of zero is connected to additional inputs of elements of OR-NOT even bits of the register of information the input of the first bit of which is connected to the information: input of the information shift block, is connected to the information output of the information shift block of the previous stage, in which the information output of the information shift block is connected to the direct output of the last bit of the shift register, the information input of the information shift block of the first stage is connected to the zero bus potential, in each cascade the output of the first OR element is connected to the first input of the zero information block, the second input of which is zero in the helmet dah, starting from the fourth, it is connected to the output of the second OR element, characterized in that, in order to increase reliability, an additional OR element is inserted into it, and an I-KE element is inserted into the information shift block of each stage, the output of which is connected to the control the output of the information shift unit, in which the inputs of the AND-NOT element are connected to the inverse outputs of the bits of the shift register, the first input of the installation. It is connected to the additional inputs of the elements OR-NOT even bits of the shift register to zero, the additional inputs of the elements OR NOT discharges, except for the first one, which is connected to the second input of the zero-shift unit 1P1formation, the inputs of the first OR element of each fuzzy cascade are connected to the control outputs of the shift blocks inform> other odd cascades, the inputs of the first OR element of each even cascade are connected to the control outputs of the shift blocks of information of other even cascades, the control outputs of the blocks of shift information of the cascades are connected to the inputs of an additional OR element, the output of which is connected to the installation input to the unit of the information shift block of the first cascade in which the installation input to the unit is connected to the installation input to the unit of the first category of the shift register, the inputs of the second element OR of each even cascade, starting from the fourth, connected to the control outputs of the information shift blocks of the previous odd cascades, the inputs of the second element OR of each odd cascade, starting from the fifth, connected to the control outputs of the information shift blocks of the previous odd digits, the second inputs of setting the shift blocks to zero information of the second and third stages are connected respectively to the control outputs of the blocks of the shift information of the first and second stages.