JP3134449B2 - Serial / parallel conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial / parallel conversion circuit, and more particularly, to a serial / parallel conversion circuit for inputting data serially from the outside and outputting all input data in parallel.
The present invention relates to a parallel conversion circuit.

[0002]

2. Description of the Related Art As a conventional serial / parallel conversion circuit, a shift register as shown in FIG. 3 is known as a circuit for inputting a serial signal in a digital signal, converting the signal into a parallel signal, and outputting the parallel signal. As shown in FIG. 3, the conventional serial-parallel conversion circuit is an n-bit shift register, and is composed of a cascade connection of flip-flops F1 to Fn, which are n master-slave D flip-flops. To the Fn clock terminals C are commonly used as serial clock input terminals CK.
Is connected.

A master-slave type D flip-flop is
When the clock supplied to the clock terminal C is "high", data is taken in from the input terminal D, and when the clock supplied to the clock terminal C changes to "low", the data taken in from the input terminal D is latched. At the same time, this data is output from the output terminal Q. When a plurality of master-slave D flip-flops are connected in cascade, data output from the output terminal Q of the preceding flip-flop is output from the output terminal Q of the subsequent flip-flop when the clock falls.
That is, the output data of the preceding flip-flop is shifted to the output of the subsequent flip-flop in synchronization with the clock.

Accordingly, the conventional serial / parallel conversion circuit shown in FIG.
Since the data supplied to the terminal IN can be successively shifted and set at the output terminals Q1 to Qn, parallel output signals are output from the output terminals Q1 to Qn and the inverted output terminals Q'1 to Q'n. be able to.

[0005]

However, the conventional serial / parallel conversion circuit described above has a problem that the number of elements required for the configuration is increased. This is because the master-slave type D flip-flop is composed of six gate circuits using one 2-input NAND gate as one gate circuit.
This requires two gate circuits.

On the other hand, in recent years, a method of transmitting serial data to each IC in the apparatus using a microcomputer or the like and setting the state of each IC has been widely used, including a DDB bus. On the side receiving such serial data, only the necessary amount of serial data is received,
In addition, a serial / parallel conversion circuit is required to control the internal circuit in parallel, and the above-described shift register is used. Therefore, in the above-described apparatus using the conventional serial-parallel conversion circuit, the number of elements required for the configuration increases, which leads to an increase in the size of the apparatus and an increase in power consumption. There is a problem.

The present invention has been made in view of the above problems, and has as its object to provide a serial-to-parallel conversion circuit capable of reducing the number of gate circuits required for configuration.

[0008]

According to the present invention, there is provided a serial communication device.
The parallel conversion circuit inputs an addressable register block and address data generated in synchronization with a serial clock, selects a register in the register block according to the address data, and stores serial data in the selected register. And the register block outputs the output of each register as parallel data as its output ,
The register includes a first NAN to which a set signal is input.
D gate and the output of this first NAND gate are input.
A second NAND gate, and a second NAND gate
The third N to which the reset output and the reset signal of negative logic are inputted.
An AND gate; and an AND gate of the second NAND gate.
An output connected to the output terminal of the register,
The output of the NAND gate is connected to the inverted output terminal of the register.
Connected and the other of the second NAND gates
It is characterized by being connected to an input terminal . Another serial-to-parallel conversion circuit according to the present invention includes an addressable register block having a data input terminal, and address data generated in synchronization with a serial clock. A decoder for selecting a register in the block,
The register block stores serial data applied to a data input terminal of a register selected by the decoder , and outputs an output of each register as parallel data.
First NAND gate to which signal and data signal are input
And the set signal and the inverted data signal are input
A second NAND gate and the first NAND gate
A third NAND gate to which an output is input;
The output of the NAND gate and the output of the second NAND gate
And a fourth NAND gate to which an output is input.
The output of the third NAND gate is an output terminal of the register.
And the output of the fourth NAND gate is
Connected to the inverted output terminal of the register and
It is characterized in that it is connected to an input terminal of a NAND gate .

[0009]

In the serial / parallel conversion circuit according to the present invention, the plurality of register blocks have a flip-flop circuit which can be constituted by two gates and a flip-flop circuit which can be constituted by one gate. The address decoder selects one register block from a plurality of register blocks connected in a matrix on the basis of the input address data, and converts the input serial data to the selected one. It can be set in the selected register block. Thus, the serial-parallel conversion circuit according to the present invention can hold the input serial data in the plurality of register blocks, and output the held data in parallel from the plurality of register blocks. The number of required gate circuits can be reduced.

[0010]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1A is a circuit diagram showing an RS register used in a serial / parallel conversion circuit according to a first embodiment of the present invention. As shown in FIG.
One input terminal of the gate G1 has a set signal input terminal S
0 is connected, the set signal input terminal S1 is connected to the other input terminal of the NAND gate G1, and one input terminal of the NAND gate G2 is connected to the output terminal of the NAND gate G1. The other input terminal of the NAND gate G2 is connected to the inverted output terminal Q ′ together with the output terminal of the NAND gate G3, and the output terminal of the NAND gate G2 is connected to the output terminal Q together with one input terminal of the NAND gate G3. I have. A negative logic reset terminal R 'is connected to the other input terminal of the NAND gate G3.

In the RS register shown in FIG. 1A, NAND gates G2 and G3 constitute a general RS flip-flop, and the set signal input side of the RS flip-flop is used. Is provided with a NAND gate G1, and selects an RS flip-flop by a set signal input from set signal input terminals S0 and S1.

FIG. 1B is a circuit diagram showing a serial / parallel conversion circuit according to a first embodiment of the present invention. The serial-to-parallel conversion circuit shown in FIG. 1B is a 16-stage serial-to-parallel conversion circuit, and the 16 register blocks F00 to F33 are the RS registers shown in FIG. Each output of the serial / parallel conversion circuit is obtained from an output terminal Q and an inverted output terminal Q ′ of each register block. The serial / parallel conversion circuit according to the first embodiment receives a serial clock from a serial clock input terminal CK, serial data from a data input terminal D, and a reset signal from a reset input terminal R '. I do. Further, the serial / parallel conversion circuit according to the first embodiment has a counter K1 which receives a serial clock and a reset signal, accumulates and outputs the serial clock, and an address decoder including decoders G4 and G5. I have.

Next, the operation of the serial / parallel conversion circuit according to the first embodiment configured as described above will be described. First, as an initial setting, a reset signal of a "low" level is applied to the reset input terminal R 'to reset the register blocks F00 to F33 and the counter K1, and then the reset is performed by setting the reset input terminal R' to a "high" level. Cancel it. Then, when the serial clock is input from the serial clock input terminal CK, the counter K1 accumulates the serial clock and outputs 2
As the converted value of the binary number, the upper two bits in the converted value of the binary number are output to the decoder G4, and the lower two bits are output to the decoder G5. The decoders G4 and G5 are provided with a counter K1.
Then, one register block is selected from the register blocks F00 to F33 based on the binary conversion value output from the register block, and data is set.

For example, when five pulses of the serial clock are input, the integrated value of the counter K1 becomes "6", and the output terminals A and C of the counter K1 become "high". As a result, the decoder G4 receives "2", and therefore, among the output terminals of the decoder G4, the output terminal Y2
Only goes high. On the other hand, the decoder G5 outputs “1”
Therefore, if the data input terminal D is "high", only the output terminal Y1 among the output terminals of the decoder G5 becomes "high". Thus, the output of the decoders G4 and G5 allows the register blocks F00 to F33 to be output.
, Only the data input terminals S0 and S1 of the register block F12 become "high", so that only the register block F12 is set with data. Here, when the data input terminal D is "low", the output of the decoder G5 does not select any of the register blocks F00 to F33, so that the register block F12
No data is set.

As described above, the serial-to-parallel conversion circuit according to the first embodiment has the register blocks F00 to F00 in the order of the input serial clock and according to the data value.
Set F33 or leave it reset,
Data can be output collectively and in parallel from the output terminals Q and Q 'of the register blocks F00 to F33. Therefore, the serial-to-parallel conversion circuit according to the first embodiment is required to be formed from a conventional serial-to-parallel conversion circuit because each register block can be formed by only three NAND gates. The number of gate circuits can be reduced.

Next, a second embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 2A shows the RS used in the serial / parallel conversion circuit according to the second embodiment.
FIG. 2B is a circuit diagram showing a register, and FIG. 2B is a circuit diagram showing a serial / parallel conversion circuit according to the second embodiment. In FIGS. 2A and 2B, FIG.
Constituent elements having the same functions as those of the first embodiment shown in (a) and (b) are denoted by the same reference numerals and description thereof is omitted.

In the RS register shown in FIG. 2A, a component different from the RS register shown in FIG. 1A has no reset input terminal R ', and instead has a data input terminal D and three input terminals. NAND gate G6 and inverter G
6 is the added portion. As a result, FIG.
When the set signal input terminals S0 and S1 are both set to "high" and this RS register is selected, the RS register shown in (1) resets the setting by the data applied to the data input terminal D. Is also possible.

FIG. 2B is a block diagram showing the serial register according to the second embodiment using the RS register shown in FIG. 2A as each of the register blocks F40 to F73.
The serial / parallel converter has a data input terminal D connected to register blocks F40 to F40.
73 is connected to each data input terminal D, and the counter K
1 is connected to the reset input terminal R 'of the serial / parallel conversion circuit, and the other configuration is the same as that of the serial input / output circuit according to the first embodiment shown in FIG.
This is the same as the parallel conversion circuit.

The operation of the serial / parallel conversion circuit according to the second embodiment is similar to that of the first embodiment except that the reset input terminal R 'of each register block is connected to the data input terminal D. Since they are connected, only an arbitrary register block can be set and reset. Further, by setting the counter K1 to a presettable type or the like, only necessary data can be fetched into only necessary register blocks, or necessary data can be overlaid and used as if it were a software register. In the serial-parallel converter according to the first embodiment, the reset input terminal R 'of the serial-parallel converter is commonly connected to the reset input terminal R' of each of the register blocks F00 to F33. F33 can reset all at once, but cannot reset only individual register blocks.

Therefore, the serial communication according to the second embodiment
The parallel conversion circuit can reduce the number of gate circuits required for its configuration and can set and reset only an arbitrary register block.

In the first and second embodiments described above,
Although the RS register is used as a register block constituting the serial / parallel conversion circuit, a T flip-flop, a D latch, a JK flip-flop, or the like can be used as a register block, and an address decoder of each register block can be used. A NAND gate, a NOR gate, or the like can also be used. In the above-described first and second embodiments, 4 × 4 = 16 register blocks are provided. However, 8 × 8 = 64 register blocks are provided in the same manner.
The design may be made using 8 × 16 = 128 and 16 × 16 = 256 register blocks.

[0023]

As described above, according to the serial / parallel conversion circuit according to the present invention, the register block for holding and outputting one data can be constituted by three gates. -A parallel conversion circuit can be used to reduce the pellet size and power consumption. For example, in the serial / parallel conversion circuit according to the present invention, the counter has 24 gates, the decoder has 12 gates, and the register block has 3 × 16 = 48.
In the case of a configuration using the number of gates, a total of 84 gates are required. In the conventional serial / parallel conversion circuit, 6 × 16 = 96 gates are required only in the register block.

In particular, in an IC having a function of generating a serial clock by itself, the serial clock according to the present invention is used.
Since the counter section of the parallel conversion circuit can also be used as the section for generating the serial clock, the amount can be substantially reduced.

In the serial / parallel conversion circuit according to the present invention, it is possible to arrange only 50 required RS flip-flops as components, for example, so that the number of gates can be further reduced. can do. This is particularly effective as the number of register blocks increases. For example, when the number of register blocks is 256, 256 × 6 = 1536 gates are conventionally required as described above. According to this serial-parallel conversion circuit, it can be composed of a total of 892 gates of 768 gates for the RS flip-flop and 124 gates for the counter and decoder. It can be configured with 58% of gates.

[Brief description of the drawings]

FIG. 1A is a circuit diagram showing an RS register used in a serial / parallel conversion circuit according to a first embodiment of the present invention, and FIG. 1B is a circuit diagram showing an RS register according to the first embodiment of the present invention; FIG. 3 is a circuit diagram illustrating a serial / parallel conversion circuit.

FIG. 2A is a circuit diagram showing an RS register used in a serial / parallel conversion circuit according to a second embodiment of the present invention, and FIG. 2B is a circuit diagram showing an RS register according to the second embodiment of the present invention; FIG. 3 is a circuit diagram illustrating a serial / parallel conversion circuit.

FIG. 3 is a circuit diagram showing an example of a conventional serial / parallel conversion circuit.

[Explanation of symbols]

F00, F01, F02, F03, F10, F11, F
12, F13, F20, F21, F22, F23, F3
0, F31, F32, F33; register blocks G1, G2, G3; NAND gates G4, G5; decoder K1;

Claims (2)

(57) [Claims] 1. An addressable register block, and address data generated in synchronization with a serial clock are input, a register in the register block is selected according to the address data, and serial data is stored in the selected register. And a decoder for storing
The register block is to output the output of each register as an output as parallel data, said Le
The register is connected to the first NAND gate to which the set signal is input.
And the first NAND gate to which the output of the first NAND gate is input.
2 NAND gates and the output of this second NAND gate.
Third NAND to which reset signal of force and negative logic is input
And the output of the second NAND gate is
The third NAN connected to the output terminal of the register;
The output of the D gate is connected to the inverted output terminal of the register.
And the other input terminal of the second NAND gate
A serial / parallel conversion circuit, which is connected to a slave . 2. A register block having a data input terminal and capable of addressing, and a decoder for inputting address data generated in synchronization with a serial clock and selecting a register in the register block according to the address data. The register block stores serial data applied to a data input terminal of a register selected by the decoder , and outputs an output of each register as parallel data.
The register receives a set signal and a data signal.
A first NAND gate, a set signal and an inverted data
A second NAND gate to which a data signal is input;
Third NAND to which the output of one NAND gate is input
A gate, an output of the third NAND gate, and the
Fourth NAND to which the output of the second NAND gate is input
And the output of the third NAND gate is
The fourth NAN connected to the output terminal of the register;
The output of the D gate is connected to the inverted output terminal of the register.
Connected to the input terminal of the third NAND gate
A serial-to-parallel conversion circuit characterized by being performed .