SU692091A1 - Reversible n-digit pulse counter - Google Patents

Description

(54) REVERSE. P-DISCHARGE IMPULSE COUNTER

Claims (1)

The invention relates to the field of impulse technology and can be used when designing reversible counters for digital computing devices. A reversible p-bit pulse counter is known, each bit of which contains seven four-three-way ternary logic elements; an installation bus and a counting bus that is connected to the first and inputs of the first ternary logic element and to the first input of the second ternary logic element; with the third input of the first ternary logical element, the output of which is connected to the first and second inputs of the third ternary logical element and to the fourth input of the fourth threefold logical element one first input coupled to O; Odom second ternary logic gate «I. A disadvantage of the known device is its complexity, since each of its bits is built on seven four-input ternary logic elements. The aim of the invention is to simplify the reversible n-bit pulse counter. For this, in a reverse n-pulse pulse counter, each row of which contains four four-input ternary logic elements, an installation bus and a counting bus, which is connected to the first and second inputs of the first ternary logic element and the first input of the second ternary logic element, the installation bus is connected with the third input of the first ternary logic element, the output of which is connected to the first and second inputs of the third ternary logic element and to the fourth entrances of the fourth ternary logical element, the first input of which is connected to the output of the second ternary logic element, in each bit of the installation bus is connected to the fourth input of the third ternary logic element, the output of which is connected to the fourth inputs of the first and second ternary logic elements, the output of the last of which is connected to the third input the fourth ternary logic element, the output of which is connected to the counting bus of the subsequent discharge. FIG. 1 shows a structural electrical circuit for a reverse TEAH pulse counter; FIG. Figure 2 shows the time diagrams of the operation of a three-bit reverse pulse counter. The four-input ternary logic elements 1, 2, 3, 4 are the first bit of the reversible pulse counter, the four-input ternary logic elements 5, 6, 8, 8, 10, the second bit of the reversible pulse counter, and the four-second ternary logic elements 9, 10, 11, 12 - the third bit of the reversible pulse counter. Drives 13: 14 15 are counting tires of the first second and third bits, respectively, and tires 16, 17, 18. are installation wise respectively lane. second, third and third bits. In each bit of the installation bus 16 (17, 18) is connected to the third input of element 1 (5., 9) and to the fourth input of element 3 (7, 10), respectively, the counting bus 13 (14 , 15) is connected to the first and second inputs of element 1 (5, 9) respectively by the first input of element 2 (6, 11). The output of element 1 (5, 9) is connected to the first and second inputs of element 3 (7, 10) and to the fourth input of element 4 (8, 12, the first and the third input of which is connected to the OUTPUT of the Element 2 ( b, 11), the fourth input of which is connected to the fourth INPUT of the element (5, 91 f. and s., output of the element 3 (7, 10). The output of the element .4 is connected to the counting bus 14 of the second bit, output. element 8 which is connected to the counting bus of the third bit. The outputs of the elements 3, 7, 10 are the outputs of the first, second and third bits, respectively. The device works as follows. C the clock theme; the meter circuit power supply is three-phase; with this, the input pulses are positive (for the case of addition) and negative (for the case of a voltage) arrive on the first discharge counting bus 13 through three phases (one clock cycle) of information transmission over the circuit elements (FIG. 2). The bias when adding is represented by a positive impulse, and when subtracting - by a negative impulse at the output of elements 4 and 8. The presence of feedback allows storing the result of the addition (subtraction), i.e. and positive-polarity pulses at its output. If necessary, before the start of the recording operation of the initial state of the meter bits, the buses of the settings 16, 17, 18 are supplied with pulses of the corresponding polarities (when recording H, a positive pulse is applied to the bit, while writing O a negative pulse). During the operation of the reversing counter, the clock of the first phase reads information from elements 5, b and 10, the second phase from elements 1, 2, 7 and 8, and the third phase reads elements 3, Л and 9. Increase pulses to the counting bus 13 the first bit during the first-phase clock pulse. . FIG. Figure 2 shows the time diagrams of the forward counting from 000 to 100 and the reverse counting of pulses from 100 to 111. - When the first pulse arrives on the bus 16 with the clock pulse of the first phase of the first cycle, according to the logic of the element, a positive signal is transmitted to the first input of element 1; the second-phase pulse, the positive signal from element 1 is transmitted to the first input of element 3 / the third phase pulse. The positive signal from element 3 is transmitted to the fourth inputs of elements 1, 2 and leaves the counter, forming the first bit. Resultant state the output of the counter is 001. When a second pulse arrives on the bus, a 16-pulse of the first phase of the second clock cycle sends a positive signal to the first input of element 1; the second phase pulse negative signal from element 2 is transmitted to the first input of element 4, the third phase pulse positive signal from element 4 is transmitted to the first input of element 5. The first phase pulse of the third cycle, the positive signal from element 5 is transmitted to the first input of element 7f by a second phase pulse the positive signal from element 7 is transmitted to the fourth INPUTS of elements 5, 6 and exits the counter, forming the second bit. The resultant state of the counter outputs is 010.. When the third pulse arrives on the bus 16 clock and pulse first phase takta.polozhitelny third signal is transmitted to the first input element 1, a positive second phase pulse signal from the element 1 is transmitted to the first input element 3; the third phase pulses a positive signal from element 3 is transmitted to the fourth inputs of elements 1, 2 and exits the counter to form the first bit. The first phase signal of the fourth cycle negative signal from eleleyite 5 is transmitted to the second input of the element 7 and to the fourth element input: 8 , from element b - the first input of element 8; the second phase pulse positive signal from element 7 is transmitted to the fourth input of elements 5, b and goes out of the counter, forming the second bit. The resultant state of the counter outputs is 011. When the fourth pulse is sent over the bus 16, the clock pulse of the first phase of the fourth cycle is a positive signal transmits to the first VX of element 1; the second phase pulse negative signal from element 2 is transmitted to the first input of element 4 by the third phase pulse and the positive signal from element 4 is transmitted to the first input of element 5. The first phase pulse of the fifth cycle. the negative signal from element 6 is transmitted to the first input of element 8 by the second pulse phase, the positive signal from element 8 is transmitted to the first input of element 9-, the third phase pulse transmits the positive signal from element 9 to the first input of element 10. The pulse of the first phase of the sixth cycle is a positive signal from The element 10 is transmitted to the fourth input of element 9 and leaves the counter, around the third bit. The resulting state of the counter outputs is 100. When the fifth pulse arrives on the bus 16 with the clock pulse of the first phase of the fifth cycle, a negative signal is transmitted to the second input of element 1 and to the first input of element 2 by the pulse of the second phase, a positive signal from the element 1 is transmitted to the first input of element 3, from element 2 to the third input of element 4; the third phase pulse positive signal from element 3 is transmitted to the fourth inputs of elements 1, 2 and exits the counter, forming the first bit, the negative signal from element 4 is transmitted to the second input of element 5 and to the first input of element 6. The positive signal from element 5 is transmitted to the first input of element 7 by the impulse of the first phase of the sixth cycle, from element 6 to the third input of element 8, the positive signal from element 7 is transmitted to the fourth inputs of elements 5, 6 and exits the counter, immediately the second bit, the negative signal from the element b is transmitted to the second input of the element 9. The resulting state of the output of the counter is 011. Upon receipt of subsequent pulses through the bus 16, the reversible counter works in a similar way. Claims of the invention A reversible p-bit pulse counter, which has four four-input EaK ternary logic elements, an installation bus and a counting bus, which is connected to the first and second inputs of the first three-dimensional logic element and the first input of the second threefold logic element, the installation bus is connected with the third input of the first ternary logic element, the output of which is connected to the first and second inputs of the third ternary logical KoFo element and to the fourth input of the fourth threefold logical element-ieHTa, the first input of which is connected to the b output of the second ternary logic element, characterized in that, for the purpose of simplification, in each bit of the installation bus is connected to the fourth input of the third Trinity logic element, the output of which is connected to the fourth inputs of the first and second Logic elements, the output of the last of which is connected to the third input of the fourth ternary logic element, the output of which is connected to the counting bus of the next bit. Information sources, . taken into account during the examination 1. Sokolov T.N. and others. Ferrite logical elements .and nodes of information systems. L., Leningrad Military Engineering Academy of the Red Banner AF Mozhaisky, 1970, p. 194-196, fig. 4.66 (prototype).  , 11tl, v) J G: N, i4 692 0-9f