SU764137A1 - Reversible pulse counter - Google Patents

Description

The invention relates to the field of impulse technology and can be used in the design of reversible counters for digital HE-OBLIGATION devices. A reversible N-bit pulse counter is known, each time & Also, it contains seven ternary logic elements 11. A disadvantage of the known device is its complexity. Known reversible counter im-. pulses, containing an input bus and N bits, each of which contains four four-input triple logic elements and an installation bus, the output of the first three-way logic element is connected to the first and second inputs of the second and fourth inputs of the third three-dimensional logic elements, the installation bus is connected to the fourth input of the second and the third input of the first ternary logic elements, the fourth input of the last of which is connected by the output of the second and the fourth input of the fourth ternary logic elements, output The last of which is connected to the first and third inputs of the third ternary logic element, the first and second inputs of the first and the first input of the fourth ternary logic element of each bit, after searching for the first three, is connected to the output of the third threefold logical element of the previous bit, and in the first Raz de - with input bus 2J. In the known device, each four-input ternary logic element is described by the following truth table. A disadvantage of the known device is its complexity: in each bit four four-input ternary logic elements are used. The purpose of the invention is to simplify the counter. To achieve this goal, in a reverse pulse counter containing an input bus and N bits, each of which contains three four-input ternary logic elements and an installation bus, the output of the first ternary logic element is connected to the first and second inputs of the second and fourth inputs of the third three-way logic elements, the fourth input of the second ternary logic element is connected to the installation

in accordance with the invention, in each discharge, the output of the second ternary logic element is connected to the first input of the first ternary logic element, the second input of which is connected. is not with the installation bus, and the third and fourth inputs are with the first input of the third ternary logic element, which is connected in each bit except the first, with the output of the third ternary logic element of the previous bit, the first input of the third ternary logic element of the first bit with input bus ,.

FIG. 1 shows a diagram of a reversive three-digit pulse counter; fig 2 shows the time

on the work diagram trehrisr d ogb

pulse counter,

FIG. 1 shows four-input ternary logic elements 1-3 of the first bit; four-way

ternary logic elements 4-6 of the second bit; Ф лог троОой ойойО тро тро тро Triple logical elements 7-9 of the third bit; entrance 10;

Installation tires 11–13 with the response of the first 6, second and third digits,.

Outputs of four-code ternary. logic elements 2, 5, 8 sootCineyi, respectively, with the first input-. 1, 4, 7, three-dimensional logical elements, 1, 4, 7 three-way logic element outputs are combined with the first 2, 5, 8 fourth-element logic elements of 4, 4 and 4

logic elements 3, .b, 9, yctanovykhanshin 11-13 are connected so. responsibly with the second entrances. ternary logic elements 1, 4, 7 and with the fourth inputs of the ternary logic elements 2, 5, 8, the input bus 10 outputs of the ternary; logic elements 3, 6 are connected respectively with the Third and fourth inputs of the threefold LOGICAL elements 1, 4, 7 and the first inputs. ternary logic elements 3, 6, t

 J:. -. , .. - ... -

The outputs of the first, second and third bits of the counter are, respectively, the outputs of elements 2, 5 and 8, the outputs of transfers of the first, second, and third bits of the counter, respectively, the outputs of elements 3, b and 9 ... Pr impulse receipt from the bus; 10 or from the outputs of the elements 3, 6, the corresponding discharge changes its internal state to the opposite. When a counter goes from state 1 to state O, at the output of elements 3, 6 or 9 a transfer pulse appears in the next one, the counter discharge. When a positive polarity pulse arrives on the bus 10, the reversible counter performs the functions of a summing counter, and when a negative pulse arrives, it functions as a subtracting counter. The transfer when added is represented by a positive impulse, and when subtracted - by a negative impulse at the output of elements 3, b and 9, the presence of a return. Own communication allows you to store the result of the addition (subtraction), t, e. Provides state storage

bit counter in the form of

pulse generation positive

polarity at its output.

When a positive pulse arrives at the installation tires 11-13, the counter discharge is set to a state; when a negative pulse arrives, elements 2, 5 and 8 compensate for the pulses of the counter discharge state, i.e. counter reset.

If it is necessary to write a code of a certain number, the setting tires 11–13 of the counter bits are supplied to the values of the bits of the recorded number.

The system of clock power scheme schefl-trehfeena.

The clock pulses of the first phase read information from elements 4 and 8, the pulse of the second phase from elements 1, 5, 6, the pulse of the third phase from elements 2, 3 and 7. The pulses go through the input bus 10 to the inputs of elements 1 and 3 during the clock first phase pulse.

FIG. Figure 2 shows the time diagram of the forward counting from 000 to 10Q and the reverse counting of pulses from 100 to

111. ; - When the first pulse arrives on the bus 10 by the clock of the first phase of the first clock, according to the element truth table, a positive signal is transmitted to the third input of element 1 and to the first input of element 3, a second phase pulse sends a negative signal from element 1 to the second input of element 2 and at the fourth input of element 3; the third phase pulse positive signal from element 2 is transmitted to the first input of element 1 and exits the counter, forming the first discharge.

The resulting state of the meter outputs is 001 ..

When the second pulse arrives on the bus 10, the clock pulse of the first phase of the second cycle transmits a positive signal to the third input of element 1 and to the first input of element 3; impulse of the third positive. The signal from element 3 is transmitted by fea to the third input of element 4 and to the first input of element 6,

The pulse of the first phase of the third cycle a negative signal from element 4 is transmitted to the second input of element 5 | and to the fourth input of element 6; impulse of the second phase positive signal from element 5 is transmitted to the first input of element 4 and exits the counter, forming the second discharge. The resultant state of the counter outputs is 010. When the third pulse arrives on the bus 10, the clock pulse of the first phase of the third cycle is transmitted to the third the input of element 1 and the first input of element 3 by the second-phase pulse a negative signal from element 1 is transmitted to the second input of element 2 and to the fourth, th input of element 3; a third phase pulse positive signal from element 2 is transmitted to the first input of element 1 and exits the counter to form the first bit. The first signal from element 4 is transmitted to the first phase of the fourth cycle; the first input of element 5 is transmitted to the first phase; the second phase pulse positive signal from element 5 is transmitted to the first input of element .4 and exits the counter, forming the second discharge. ; ; The resultant state of the counter outputs is 011. When the fourth pulse arrives on the bus 10, the clock pulse of the first phase of the fourth clock cycle transmits a positive signal to the third input of element 1 and to the first input of element 3; the third phase pulse positive signal from element 3 is transmitted to the third input of element 4 and to the first input of element 6. The second phase pulse of the fifth cycle is a positive signal from element b is transmitted to the third input of element 7; By the third phase pulse, the negative signal from element 7 is transmitted to the secondary: input of element 8.. The pulse of the first phase of the sixth cycle positive signal from element 8 is transmitted to the first input of element 7 and exits the counter, forming the third bit. The resultant state of the counter outputs is 100. When the fifth pulse is received, the bus 10 clock pulse of the first phase of the fifth cycle a negative signal is transmitted to the fourth input of element 1; a second-phase pulse with a negative signal from element 1 is transmitted to the input of element 2 and to the fourth input of element 3; the third phase pulse positive signal from element 2 is transmitted to the first input of element 1 and exits the counter, forming the first bit, the negative signal from element 3 is transmitted to the fourth input of element 4. By the first phase pulse of the sixth cycle the negative signal from element 4 is transmitted to the second input element 5 and the fourth input element 6; The second phase impulse positive signal from element 5 is transmitted to the first input of element 4 and-exits from the switch, forming the second bit, a negative signal from element b is transmitted to the fourth input of element 7. The output state of the counter is Oil. Upon receipt of subsequent pulses on the bus 10 reversible counter works the same way.

7641378

Table continuation

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Claims (2)

1.Sokolov T.N. and others. Ferritic logical elements and informational nodes. L., Leningrad State Military University of the Red Banner of the Academy. A.F. Mozhaysky, 1970, with. 194-196, fig. 4.66. 2. USSR author's certificate on application 2520229 / 18-21, cl. H 03 K 23/00, 02.20.78 (prototype)