SU1324109A1 - Reversible pulse counter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in the design of reversible counters for digital computing devices with a binary number system. The invention provides an increase in the speed of the counter, made according to the scheme shown in the drawing. The counter contains ternary elements 1-6 of the first bit, ternary elements 7-12 of the second bit, input bus 13, clocking buses 14 and 15 of the first and second bits, respectively. The operations performed by the ternary elements are explained in the table provided in the description of the invention. The first and second summing (subtracting) inputs of all ternary elements are equivalent. The system of clock supply of the counter is three-phase. The binary number system 1.01 is used to represent the numbers in the counter. The sign of the number is determined by the sign of the most significant bit. In the proposed counter, the pth bit is generated in 1 + n clock feed phases. ., 1 tab. Q (L oo rsD 4 O CO

Description

The invention relates to a pulse technique and can be used in the design of reversible counters for digital computing devices with a binary number system.

The aim of the invention is to increase speed.

FIG. 1 is a diagram of a two-bit reversible pulse counter; figure 2 - the timing diagram of his work.

The counter (Fig. 1) contains ternary elements 1-6 of the first bit, ternary elements 7-12 of the second bit, input bus 13, clocking buses 14 and 15 of the first and second bits, respectively. The tire 13 is connected to the first summing and second subtractive inputs of elements 1 and 2, the second summing input of element 3 and the first summing input of element 4. Tires 14 and 15 are connected to the first subtractive inputs of elements 3, 4 and 9,

10 respectively, as elements

1, 2, 7 and 8 are connected to the first computational inputs of elements 5, 6, 11 and 12, respectively. The output of element 3 is connected to the first and second summing inputs of elements 6, 7, respectively, the second subtractive input of element 8 and the second summing input element 9. The output of element 4 is connected to the first summing inputs of elements 5, 8 and 10 and the second subtracting input element 7. The outputs of elements 9 and 10 are connected to the first summing inputs of elements 12 and 11, respectively. The output of element 5 is connected to the first subtractive input of element 1 and the second subtractive inputs of elements 2 and 4. The output of element 6 is connected to the second summing input of element 1, the first subtractive input of element 2 and the first summing input of element 3. The output of element

11 is connected to the first subtractive input of the element 7 and the second summing inputs of elements 8 and 10. The output of the element 12 is connected to the first summing input of the element 8 and the first summing input of the element 9.

In Fig. 2, timing diagrams 16-18 are indicated, respectively, of the first to third phases of the clock supply; timing diagram of 19 pulses on bus 13; timing charts 20-31

.-

O

five

0

pulses on the highs of elements 1-12, respectively.

The system of clock supply of the counter is three-phase. The positive and negative pulses are fed to the bus 13 by the first-phase pulse and the pulse is supplied with a clock frequency of the inflator 14 and 15, and the information from elements 11 and 12 is read, the clock and the pulses of the second and third phases are read from the elements 1-4 and 5-10 respectively. Each next pulse enters the bus 13 through a time multiple of three phases.

The counter is executed on ternary elements that perform the operations described by the table. The first and second summing (subtracting) inputs are equivalent to each other.

35

45

50

On elements 1 (7) and 5 (11) negative pulses of state +1 are formed, and on elements 2 (8) and 6 (12) negative pulses of –1 –1 of the first (second) digit of the counter are formed. On the element 4 (10) a positive transfer pulse +1 is formed, and on the element 3 (9) a positive transfer pulse -1 of the first (second) digit of the counter is formed.

To represent the numbers in the counter, a binary number system with the numbers 1, 0, 1 is used, and the sign of the number is determined by the sign of the most significant digit.

313

The arrival of a positive pulse to the input bus 13 adds a positive unit to the contents of the counter, the arrival of a negative pulse -1 adds a negative unit. If the counter is in the zero state, the first positive pulse sets the first bit to the +1 state, the second positive pulse sets the first bit to the O state, and passes through the transfer output (positive pulse from element 4) to the next second bit. the bit sets its state to - 1, and so on. The arrival of negative pulses at the input bus 13 causes a consecutive decrease of the accumulated number in a non-positive number, and then, after crossing zero, the accumulation of a negative number. The presence of feedback allows you to store the result of the addition (subtraction), i.e. provides storage of the +1 (-1) state of the counter in the form of generation of negative polarity pulses at its outputs. The state +1 of the first (second) counter is removed as a negative pulse from the output of element 5 (11), and state -1 in the form of a negative pulse from the output of element 6 (12).

To reset the counter, it is necessary to enter a zero reset bus connected to the second summing inputs of elements 5, 6, 11 and 12, when a pulse arrives at which the discharge state pulses are compensated, i.e. zeroing.

When writing a code of a certain number, it is necessary to enter into each discharge an installation bus connected to the second subtractive inputs of elements 5 and 6 (11 and 12). The installation tires are supplied with the digits of the recorded number.

Figure 2 shows the timing diagram of the counter for the cases of direct counting from 0 to 3, o (from 00 to llj) and reverse counting from +3, to -3., O (from llj to Tij).

The device works as follows.

When the first positive pulse arrives on the input bus 13 with the clock pulse of the first phase of the first clock cycle, according to the logic of the element recorded in the table, put 094

A solid pulse is transmitted to the second subtractive input of element 1 and the first summing inputs of elements 2 and 4, and positive pulses through buses 14 and 15 to the first subtractive inputs of elements 3, 4 and 9, 10, respectively. The second phase pulse negative pulse from element 1 is transmitted to the nepBbtfi subtracting input of element 5. The third phase pulse from negative element 5 is transmitted to the first subtractive input of element 1 and the second summing inputs of elements 2 and 4. The first phase pulse of the second cycle from elements 11 and 12 pulse information is not read. The resulting status of the outputs of the counter 01.

When the second positive pulse arrives at the pin 13 with the clock pulse of the first phase of the second cycle, a positive pulse is transmitted to the second subtractive input of element 1 and the first summing inputs of elements 2 and 4, and the positive impulses through buses 14 and 15 to the first subtractive inputs of elements 3, 4 and 9, 10 respectively. The second phase pulse sends a negative pulse from the element to the first subtractive input of element 5, and a positive pulse from element 4 is transmitted to the first summing inputs of elements 5, 8 and 10 and to the second subtracting input of element 7. The third phase pulse from the negative element 7 is transmitted to the first subtractive input of the element 11. The pulse of the first phase of the third cycle from element 11 reads a negative pulse. The resulting status of the outputs of the counter lOj.

Upon receipt of subsequent pulses on the input bus 13, the counter operates in a similar way.

In the proposed counter, the pth bit is formed in the 1 + n phase of the clock supply.

Claims (1)

Claim 1. Counter pulse counter, containing the input bus and bits, each of which contains six ternary elements, the first summing input of the first ternary element is connected to the first summing input of the second ternary element, the output of the third ternary element is connected to the first summing input of the fourth of the ternary element, the outputs of the fourth and fifth ternary elements are connected to the first subtractive inputs of the first and sixth ternary elements, respectively, in each bit of the first, but the first summing input of the first ternary element is connected to the output of the second ternary element of the previous bit, the input bus connected to the first summing inputs of the first and sixth ternary elements of the first bit, which is due to the fact that, in order to increase speed, a clocking bus is inserted in each bit, which united with the first subtractive inputs of the second and third loop elements; the outputs of the first, second and sixth ternary elements are connected to the first subtractive input of the fourth, first, summing input of that and the first subtractive input of that ternary elements respectively; the output of the fourth threefold element is connected to the first summarize1324109 t with d , no tr with in JO ME WH VU di (5 tr 20 in no harm 25 what / 7 GW 19 go r1 22 gz 24 25 26 27 28 g9 50 / -IL so gooby inpuAsy f schipybone, -f "Ik ,. CCHTI: o e, / VNIIPI Order 2972/56 Random polygons pr-tie, Uzhgorod, st. Project, 4 the third input of the third ternary element, the output of the fifth ternary element is connected to the second summing inputs of the first and second ternary elements, the second subtracting input of the first and the second summing input of the third ternary elements are interconnected, in each bit, except the first, the output of the fourth three The element is connected to the first summing input of the sixth ternary element, the second summing input of which is connected to the second subtractive input of the first threefold element and to the output 5 of the third ternary element of the previous discharge, the output of the second ternary element of which is connected to the second subtractive input of the sixth ternary element of the previous discharge, 0 in the first discharge, the input bus is connected to the second subtractive inputs of the first ternary element and the sixth ternary element, the second summing input of which is connected to the output 5 fourth ternary element. SCHITYBACHNV O VOP1 / S, f Sonuct, -1  Rie.g. Circulation 901 Subscription