SU440795A1 - Reversible binary counter - Google Patents

Description

one

The proposed device relates to the field of automation and computer technology, where it can be used to build various automatic and computing units (counting the number of products manufactured, building various nodes of digital computers, etc.).

In known cxeiMax reversible binary counters, the amount of equipment increases in proportion to the number of bits of the counter.

The purpose of the invention is to build a simple scheme of a reversible binary counter of large capacity, the equipment of which practically does not depend on the number of bits.

This is achieved by performing a correction circuit that analyzes the previous state of the counter and operates according to an algorithm;

when there is no input pulse, the reverse binary counter information is circulated without change;

When the input pulse arrives, the content of the reverse binary counter is inverted (starting from the lower bits) to the first zero (addition mode) or to the first unit (subtraction mode), inclusive, and the rest of the number (high bits) is passed without change.

The difference in the proposed scheme is the use in its composition of a special circuit for synchronizing the circulation of a dynamic register that performs the functions of the missing summing element.

The drawing shows a functional diagram of a reversible binary counter.

A reversible binary counter consists of a dynamic register 1, an inverter 2, a matching circuit 3 and 4, a separation circuit 5, a sign trigger 6, and a dynamic register circulation synchronization circuit consisting of an input trigger 7, a delay element 8, an input signal synchronization circuit 9 , separation schemes 10 and match schemes And 12.

The synchronization circuit of the input signal 9 is necessary to generate the signal PI (low-order) of the dynamic register 1 and the clocking of the input pulses by these signals. This is necessary in order to

In case of arrival of the input pulse, the contents of the dynamic register were processed starting from the lower order.

If the counting pulses do not arrive at the circuit input, then the trigger of the input signal 7 is in the zero state and the code recorded in the dynamic register 1 circulates through the circuit: output of the dynamic register 1, coincidence circuit 3, dividing circuit 5, input of the dynamic register. The code units passing through the coincidence circuit 11 (if the sign trig is in the zero state), the separation circuit 10 and the delay element 8 confirm the zero state of the trigger of the input signal 7.

When a counting pulse is applied to the input of the " + sign trigger 6 and the trigger of the input signal 7 are set to one. At the same time, coincidence circuits 3 and II are closed, and circuits 4 and 12 are opened, and the code from dynamic register 1, starting with the lower order bit, will pass through inverter 2 and coincidence circuit 4. The first zero of the code recorded in dynamic register 1, inverted is written through the separation circuit 5 to the dynamic register 1 unit, and also, having passed the matching circuit 12, the separation circuit 10 and the delay element 8, flips the trigger of the input signal 7 to the zero state.

This closes the matching circuit 4 and opens the matching circuit 3, and the other high-order bits are overwritten into the dynamic register without change. The delay element for a poltakt is necessary for accurate operation of the circuit. As a result, the code in the dynamic register will increase by one. If the next input pulse arrives on the same "+" bus, the cycle is similarly repeated, and the code is increased by one more.

In the case of the arrival of a counting pulse on the subtraction bus, the character 6 trigger flips to the zero state, and the input signal trigger 7 goes to the single state. This closes the matching schemes 3 and 12,

and diagrams 4 and 11 open. The first lower unit of the code recorded in the dynamic register 1, having been inverted by inverter 2, is written to the dynamic register with zero, and also, having passed the coincidence circuit 11, the separation circuit 10 and the delay element 8, flips the trigger of the input signal 7 to the zero state. This closes the matching circuit 4, opens the matching circuit 3, and the other high-order bits are overwritten without change. As a result, the code in the dynamic register is decremented by one.

Subject invention

A reversible binary counter containing a dynamic register, coincidence and separation circuits, an inverter and a character trigger whose outputs are connected to the first inputs of a dynamic register circulation synchronization circuit, characterized in that, for the sake of simplicity, the output of the dynamic register is connected to the second circuits synchronization circuit input dynamic register, with one input of the first coincidence circuit and through an inverter with one input of the second coincidence circuit, the outputs of these coincidence circuits are connected to the input via a separation circuit ynamic register, the other inputs of the first and second coincidence circuits connected to the outputs of the clock circuit loop dynamic tion register and the output of the second coincidence circuit is connected to the third input of the synchronization circuit loop dynamic register tion.