SU444180A1 - Device for comparing binary numbers - Google Patents

Description

(54) DEVICE FOR COMPARISON OF BINARY NUMBERS

one

The invention relates to automation 1 and digital computer technology and can be used, for example, in process control systems, ambient control systems for complexly solving the comparison of numbers presented in a parallel way.,

Comparison devices are known for obtaining individual results, the largest, smallest numbers, the largest difference. However, these devices do not allow to obtain the value of the smallest difference, and also do not provide a comprehensive solution, which simultaneously determines all four of the specified digital results.

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The chain of the invention is the creation of a simple device with enhanced functionalities for comparing binary numbers represented in a parallel way, in which the full cycle of working out the algorithm of its functioning as comparison rules is defined as extreme values as compared numbers so. and their differences. I

To achieve this goal in the proposed device, the comparison of the outputs of the third and fourth circuits AND through the sixth circuit OR are connected to the input of the first counting counter, and the other inputs of the third and fourth circuits AND to the outputs of the fifth and sixth circuits AND, one of the inputs. associated with the first inputs of the two seventh circuits And and with the outputs of the first trigger, the counting input of which is connected with the second, rymi inputs of both the seventh And circuits, the output of the third OR circuit, the first input of the eighth And circuit, and one of the separate inputs of the second trigger , other entrances of pto and six CJSSM AND are connected to the input of the second summing counter and with the output of the ninth And circuit, the outputs of the seventh and eighth circuits And are connected to the reset buses, respectively, of the reversing and first summing counters, the first input of the ninth And circuit is connected to the forward output of the second trigger . pa, the other input of which is connected to the input bus of the device, and the inverse output of one of the inputs of the tenth circuit AND,

the output of which is connected to the input of the third summing counter, and its other input and another input of the ninth AND circuit are connected to the output of the eleventh And circuit, one of the inputs of which is connected to the output of the second And circuit, and the other to the other input of the eighth And circuit, the output of the second circuit OR, and with the input of the fourth summing counter.

The drawing shows a block diagram of a device for comparing binary numbers.

The device contains subtractive counters 1, 2 and 3 compared numbers with subtractive counting input, the first 4 and. second 5 reversible counters; the first 6 and second 7 summing counters (minimum and maximum differences) with a summing counting input; the third 8 and the fourth 9 summing counters (the lowest and largest numbers) with a summing counting input; the first scheme OR 1O; differentiating circuit 11; the first circuit And 12, the generator of counting pulses 13; the second circuit And 14; second circuit OR 15; the sixth scheme OR 16; eighth scheme, And 17; fourth cxeN-iy RSH 18; fifth circuit OR 19; the third circuit And 20; seventh schemes And 21, 22; fourth circuit And 23; the first control trigger with a counting input 24; a second control trigger 25 with separate inputs; the third circuit, the fifth 27 and the sixth 28 circuit And, the ninth 29, tenth 30 eleventh 31 circuit And, the input terminal 32 devices.

The device operates as follows. In the initial state, the compared numbers are recorded in counters 1-3. There are signals at the outputs of each of the circuits 10 and therefore at the second inputs of each of the circuits 12 and at the output of the circuit 15, as well as at the second inputs of the circuits 17 and 31. The first and second control triggers are in the state where their single outputs have signals. Units are recorded in each of the bits of counters 4 and 5.

After the spreading signal arrives at terminal 32, the pulses from the generator 13 through the circuit 14 and the circuit 12 arrive at the information inputs of counters 1-3, reducing their content. At the same time, the pulses through the circuits 14 and 31 enter the counter of the largest la 9 and count in it. From the output of the circuit .and 31 pulses arrive at the second input of the circuit and the DA. Since when I is applied to terminal 32, the enabling signal i sets the trigger 25 to the state when the signal appears at its zero output, therefore, at the first input of the circuit AND AOR, pulses through this circuit pass into the counter 8 of the smallest numbers and counts in it.

After the number of pulses in the circuit is equal to the smallest number, the contents of one (or several) counters 1-3 become zero, the signal from the output of the corresponding circuit 10 disappears, and therefore the signal at the second input of the corresponding circuit OR 12. The pulses pass into these counters is terminated. The disappearance of the signal at the output of the circuit Y is fixed by the corresponding differentiating circuit 11, the pulse from the output of which through the circuit OR 26 transfers the trigger 25 to the initial state, as a result of which the signal appears at the first input of the circuit 29, the signal from the first input of the circuit 29 is removed. AOR, and the counting of pulses in the lowest number counter 9 stops. The pulse from the output of the OR circuit 26 transfers the trigger 24 to the state at which a signal appears at its zero output, therefore, at the second input of the OR circuit 27 and the first input of the circuit AND 22. The pulse from the output of the circuit OR 26 is fed to the second inputs of the circuit Both 21 and 22, goes through circuit 22, clearing counter 5, which closes circuit 23.

Since the signal at the first input 29 is transmitted, the counting pulses from the output of the AND 31 circuit through the AND 29 circuit begin to arrive at the information input of the maximum difference counter 7 and are counted therein. At the same time, the counting pulses from the output of the AND 29 circuit arrive at the first inputs of the AND 27 and 28 circuits. When a signal appears at the second input of the AND 27 circuit and from the output of the OR 18 circuit to the first input of the AND 20 circuit, the pulses through the circuits And 27 and 20 pass t to the summing input of the counter 5, calculated in it. In this case, the AND 23 circuit opens and the pulses of the input to the subtracting input of counter 4 reduce its content, and also through the circuit OR 16 are counted in the counter 6 of the minimum difference.

After the number following the smallest of the compared numbers goes to Zero, the signal from the output one of the OR 1O schemes disappears and the corresponding AND 12 scheme closes, terminating

 the arrival of subtractive pulses in this counter.

j The disappearance of the signal at the output of the OR 10 circuit is fixed by the corresponding differentiating circuit 11, the pulse from the output of which through the OR circuit 26 confirms the state of the trigger 25 and transfers the trigger 24 to the opposite state, as a result of which signals appear at the first input of the circuit 21 and 21 the second input of the AND 28 circuit. The pulses from the output of the OR circuit 26 are fed to the second input of the AND 21 circuit, pass through the AND 21 circuit, clearing counter 4, thereby closing the AND 2O circuit and, passing through the AND 17 circuit, clears the-6 counter minimum difference impulses with the output of the circuit AND 29 through the circuits AND 28 and 23 are read in the reversible counter 4 and through the circuit OR 16 - into the sum counter 6 and subtracted from the contents of the reversing counter 5.

If the number of pulses entering the circuit from the time when one or several compared numbers, recorded by differentiating circuit 11, zero, to the time of 1 second of the next one (or several) compared numbers, also recorded by differential circuit 11 (t, e. current difference value

numbers being compared), less than or equal to the decrement recorded in one of the reversible counters 4 or 5 (in this case, counter 5), then no switchings occur in the circuit in this time interval. This difference, as the smallest of all previous ones, will be recorded in summing counter 6. If the next current difference is more diminishing, then the time at which the number of pulses received in the circuit, the previous value of the difference, is equal, the contents of the register decremented ( If the counter 5) becomes zero, the AND circuit 14 is closed, and further flow: the pulse to the device will stop. The previous value of the difference in quality of the smallest of all compared to this point will be restored in the scheme And 22 and stored.

After the largest of all numbers vanishes, the signal from the output of the circuit disappears: OR 15, i.e., the signal at the second inputs of AND 31 and 17, the flow of pulses to the counters 9. and 7 stop, and the pulse from the output of the circuit OR 26 does not reset the contents of counter 6 to zero. Thus, in counters 9 and 8 the largest and smallest of the compared

and 6 is maximum

numbers, in counters 7 the difference of numbers.

Subject invention

A device for comparing binary numbers containing Q binary subtractive counters, the outputs of each of which are connected through OR of one of the inputs of the first AND diagrams, with other inputs connected with the output of the second AND circuit connected with one of the inputs to the generator output, and with the inputs the second OR circuit, and through the differentiating circuits | pi with the inputs of the third OR circuit, the outputs of the first AND circuits are connected to the information inputs of the corresponding subtractive counters, two reversible counters, whose outputs are connected to the inputs of the fourth and fifth IL circuits And the inputs of the addition are with the outputs of the third and fourth circuits AND, one of the inputs of which is connected to the outputs of the fifth and fourth circuits OR, respectively, the output of the third AND circuit is also connected to the subtracting input of the second reversible counter, and the output of the fourth AND circuit to the input of subtraction the first reversible counter, four summing counters, triggers, AND, OR circuits, characterized in that, in order to expand the functionality, therein, the outputs of the third and fourth circuits AND, through the sixth OR circuit, are connected to the input of the first summing account Ica, and other inputs of the third and fourth AND gates - to the outputs of the fifth and schestoy AND circuits, and one

inputs associated with the first inputs of the two seventh And circuits and the outputs of the first trigger, the counting input of which is connected with the second inputs of both the seventh And circuits, the output of the third circuit OR the first input of the eighth And circuit and one of the separate inputs of the second trigger, the other inputs n The second and sixth circuits And are connected to the input of the second summing counter and with the output of the ninth And circuit, the outputs of the seventh and eighth circuits And are connected, to the reset buses, respectively, reversible and the first summing counters, the first input of the ninth And circuit is connected to the direct output d m of the second trigger, the other input of which is connected to the device input bus, and the inverse output — to one of the inputs of the tenth AND circuit, the output of which is connected to the input of the third summing counter, and its other input and the other input of the ninth AND circuit the house of the eleventh circuit AND, one of the inputs of which is connected to the output of the second circuit AND, and the other to the other input 444180 b of the eighth circuit AND, to the output of the second circuit; we are OR, and with the input of the fourth totalizer.

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