SU1160561A1 - Ternary forward-backward counter - Google Patents

Description

The invention relates to a pulse technique and can be used in the design of ternary reversible counters · digital computing devices with ternary 5

number system. .

A ternary reversive pulse counter is known, containing an input bus and counting bits, each of which contains an installation bus, 10 zeroing bus, and six ternary elements.

The disadvantages of this device are the relative complexity and low speed.

A known ternary reversible pulse counter containing a counting bus and counting bits, each of which contains an installation and Clock tires, a zeroing bus and six ternary elements, the counting bus is connected to the first summing inputs of the first and second ternary elements of the first counting digit, ^ 5 in ' each counting bit clock bus is connected to the first subtractive inputs of the first and second ternary elements, the outputs of which are connected respectively to the first summing and first subtractive inputs of the third ternary They are connected to the first summing inputs of the first and second ternary elements of the subsequent counting discharge, in each discharge 35 the outputs of the first and second ternary elements are connected respectively to the first subtractive and summing 'inputs of the fourth threefold element, the output of which is connected to the first summing, and subtractive inputs of the fifth and sixth ternary elements, the outputs of which are connected respectively with the second summing inputs of the first and second ternary elements of the third ternary output The second element is connected to the second summing inputs of the fifth and sixth ternary elements, the second subtractive inputs of which are connected to the zeroing bus, the second summing and subtracting _(the inputs of the third ternary element are connected to the installation bus [2].

The known counter has low reliability, since each counting digit contains a large amount of equipment — six ternary elements with twenty inter-element connections.

The purpose of the invention is to increase the reliability of the counter.

This goal is achieved by the fact that in the ternary reversible pulse counter containing a counting bus and counting bits, each of which contains an installation and clock tires, a zeroing bus and three ternary elements, the counting bus is connected to the first summing inputs of the first and second ternary elements of the first counting digit , in each counting discharge, the clock bus is connected to the first subtractive inputs of the first and second ternary elements, the outputs of which are connected respectively to the first summing and first subtractive inputs Dami of the third ternary element, as well as connected respectively with the first summing inputs of the first and second ternary elements of the subsequent counting discharge, in each counting discharge the installation bus is connected to the second summing inputs of the first and second ternary elements, the second subtractive inputs of which are connected to the resetting bus , and - third summing inputs - with the output of the third ternary element, the second, third summing and second, third subtractive inputs of which are connected respectively to the outputs of the first and second th ternary elements.

FIG. 1 shows the scheme of the ternary reversible two-digit pulse counter; in fig. 2 ternary element; in fig. 3 is a timing diagram of the operation of the counter with the legend.

The counter (Fig. 1) contains ternary elements 1-3 of the first counting discharge, ternary elements 4-6 of the second counting discharge, counting bus 7, mounting tire 8, zeroing bus 9 and clock bus 10 of the first counting discharge, mounting bus 11, bus' 12 zeroing and clock bus 13 of the second counting digit.

The ternary element (Fig. 2) contains the first, second and third summing inputs 14 to 16, respectively, the third, second and first subtractive inputs 17 to 19, respectively, and output 20.

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the counting bus 7 "causes a successive decrease of the positive number accumulated in the counter, and then after going through zero 5, the accumulation of a negative number. The presence of feedback allows you to store the result of addition (subtraction), ie, it stores the" +1 "and" - 1 "counting discharge 10 counter in the form of generation of pulses of positive and negative polarity. The state of the first counting discharge is removed from the output of element 3, and the second from the output (5 element 6.

Upon admission to the tires 9 and 12 reset by one positive impulse, the counter is reset.

2o When arriving at the installation tires 8 and 11, by one positive impulse, the counting digits are set to the “+1” state, when negative impulses 25 are received to the state I ¹ '.

If it is necessary to write the code of a certain number, the installation buses 8 and 11 are supplied with the digits of the recorded number.

The counter is made on ternary magnetic logic elements, each of which performs the operations described by the table, forming a functionally complete system of logical

Counting bus 7 (Fig. 1) is connected with the first folding inputs of ternary elements 1 and 2, clock bus 10 with the first subtractive inputs of elements 1 and 2, clock bus 13 with the first subtractive inputs of elements 4 and 5, the outputs of which are connected respectively with the first summing and subtracting inputs of element 6, the outputs of elements 1 and 2 are connected respectively to the first summing and subtracting inputs of element 3 and to the first summing inputs of elements 4 and 5, the installation buses 8 and 11 are connected respectively to the second summing inputs of elements 1, 4 and with the second summing inputs of elements 2 and 5, the second subtractive inputs of which are connected respectively to the zeroing buses 9 and 12, which are connected to the second subtractive inputs of elements 1 and 4, · the third summing inputs of elements 1 and 2 are connected to the output of the element 3, the second summing and subtracting inputs of which are connected respectively to the third summing and subtractive inputs of element 3 and connected to the outputs of elements 1 and 2, the third summing inputs of elements 4 and 5 are connected to the outputs of element 6, the second summing and. the inputs of which are connected respectively to the third summing and subtracting inputs of the element 3 and connected to the outputs of the elements 4 and 5.

For the representation of numbers in the counter, the ternary notation with a symmetric arrangement is used. the numbers (+1.0, -1), where the sign of the number is determined by the sign of the most significant digit. The arrival of a positive pulse on the counting bus 7 adds a positive 45 units to the contents of the counter, the arrival of a negative pulse adds a negative one. If the counter is in the zero state, the first positive impulse will set the first 50 counting discharge to the state ”+ 1 ^m , the second positive will transfer it to the state“ -1 ”and, passing through the transfer output (positive signal from the output of element 2) to the next ( second) the counting discharge, set it to the state "+ 1", etc. Receive negative pulses on

• functions. The number of pulses (ίΐ) condition incoming at the entrances output folding subtractive 0 0 0 one one . - 0  2 2 θ 3 w · 0 one • »0 . +1 2 0.1 +1 3 .0,1,2 + 1 0 one -one 0.1 .2 -one 0,1,2 3 -one —_____ _{t τ - πΓΓΓ} 5..

five

1160561

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FIG. 3 denotes: timing charts 21–23 clock pulses, respectively, on the tires of the first, second, and third phases of the clock supply of the meter: timing diagram 24 signals 5 on bus 7; timing diagrams 25 - 30 signals, respectively, at the outputs of elements 1-6.

The system of clock power supply counter three-phase. At the same time, each barely-1® blowing pulse arrives on the counting bus through three phases (one clock cycle) of transmitting information on the counter elements (Fig. 3).

The clock pulse of the first phase reads information from element 6 and receives impulses to buses 7 and 10, the second phase reads information from elements 1 and 2 and receives impulses to the bus. 13, the third phase reads information from elements 3-5. The tires Yu and 13 always receive pulses with a clock frequency.

FIG. 3 shows the timing diagram of the direct counting from 0 _4о to +4 ₁₀ 25

(from 00¾ to 11¾) and the counting of pulses from + 4ad to -1 ₁₀ (from 11¾ to 01 ₅ ).

The clock pulse of the first phase of the first cycle according to the logic of the element recorded in the table, the positive signal is fed through bus 7 to the first summing input of element 2, while the positive signal goes through bus 10 to the first subtractive inputs of elements 1 and 2; the second-phase pulse a negative signal from element 1 is transmitted to the first summing input of element 3,

. at the same time, the positive signal goes through bus 13 to the first subtractive ₄ inputs of elements 4 and 5; the third phase pulse positive signal from element 3 is transmitted to the third summing input element 2 and exits the counter, forming the first discharge, while negative signals from elements 4 and 5 are transmitted respectively to the first summing and first subtractive inputs of element 6.

The resulting state of the outputs of the counter 01.

The clock pulse of the first phase of the second clock cycle receives a positive signal through bus 7 to the first summing input of element 2, while the positive signal goes through bus 10 to the first subtractive inputs of elements 1 and 2; the second phase impulse negative signal from element 1 is transmitted to the first summing input of element 3, and a positive signal from element 2 is transmitted to the second, third subtractive inputs of element 3 and the first summing input of element 5, while the positive signal goes through bus 13 to the first subtractive inputs elements 4 and 5; the third phase impulse negative signal from element 3 leaves the counter, forming the first digit, while the negative signal from element 4 is transmitted to the first summing input of element 6. The first-phase clock pulse of the third cycle of the positive signal from element 6 leaves the counter, forming the second digit.

The resulting state of the outputs of the counter 11.

Upon receipt of subsequent pulses on the counting bus 7, the operation of the ternary reversible counter occurs in a similar way.

The use of the proposed counter provides, in comparison with the known technical solution, the simplification of each discharge of the counter into three ternary elements and four inter-element connections, which increases the reliability of the proposed device.

1160561

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15'– 16 ’

17 - 18

nineteen -

+ N

+ N

+ N

+ and

+ n

+ .N

20

2

1160561

three-phase power supply pulses

recording 71 "recording, .- G c chit6ing„ 0 "

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read-G FIG. 3

Claims (1)

THIRD REVERSING COUNTER of impulses containing counting bus and counting bits, each of which contains the installation and clock tires, zeroing bus and three ternary elements, the counting bus is connected to the first summing inputs of the first and second ternary elements of the first counting discharge, in each counting digit the clock bus is connected to the first subtractive inputs the first and second ternary elements, the outputs of which are connected respectively with. the first [Summing and> first subtractive inputs of the third, ternary element, and also connected respectively to the first summing inputs of the first and second ternary elements of the subsequent counting discharge, which is different from me in that, in order to increase reliability, in each counting digit the installation bus is connected with the second summing inputs of the first AND second ternary elements, the second subtractive inputs of which are connected to the zeroing bus, and the third summing inputs with the output of the third ternary element, the second, third summing The second and third subtractive inputs of which are connected respectively to the outputs of the first and second ternary elements. „, Δυ ,,, ιΐ 160561 > 1160561 2