SU767753A1

SU767753A1 - Number comparator

Info

Publication number: SU767753A1
Application number: SU782632183A
Authority: SU
Inventors: Михаил Алексеевич Дуда; Роман Алексеевич Дуда
Original assignee: Ордена Ленина Институт Кибернетики
Priority date: 1978-06-19
Filing date: 1978-06-19
Publication date: 1980-09-30

Description

Изобретение относитс к области авюматики и вычислительной техники и может быть использовано при р1еализа- ции технических средств цифровых систем контрол и обработки информации. Известно устройство дл сравнени чисел, содержащее регистры, триггеры, схему сравнени , логические элементы И, ИЛИ, элементы задержки fll. Это устройстбоможет определ ть наибольшее или наименьшее из следующих друг за другом чисел, заданных последовател ност ми импульсов. Однако устройство не можё осуществл ть одновременно выборку наибольшего и наименьшего из этих чисел, определ ть разность между ними, а также осуществл ть допусковый контроль за непрерывным процессом или числами, заданными импульсными последовательност ми . Наиболее близким к предложенному по. технической сущности вл етс устройство , содержагцее первый и второй регистры с суммирующим счетным вхоДОМ , реверсивный счетчиК( схемы сравнени , триггеры, группы элементов И, дешифраторы, логические элементы И, ИЛИ, НЕ, элементы задержки, в котором выходы разр дов первого регистра соединены со входами первой схемы сравнени и со входами соответствующих разр дов реверсивного счетчика через первую группу элементов И, другие входы которых соединены через первый элемент задержки с шиной сброса реверсивного счетчика, выходы разр дов которого соединены со вторыми входами первой и второй схем сравнени , с выходами первого элемента ИЛИ, выход которого подключен к входу элемента НЕ, и со входами соответствующих разр дов второго регистра через вторую группу элементов И выходы разр дов второго регистра соединены со входами второй схемы сравнени , перва шина управлени и шина сброса соединены через второй элемент ИЛИ с первыми входами третьей группы элементов И, причем ши3 на сброса соединена через второй элемент задержки с входЬм третьего эле мент.а задержки, пр мые и инверсные выходы первого и второго триггеров соединены с соответствующими входами третьей группы элементов И 2. В эток устройстве выходы схем сравнени св заны со счетнь1ми входами двух триггеров , а информационный вход устройства подключен к счетному входу реверсивног счетчика. Недостатком этого устройства вл ет то, что оно не может осуществл ть выборку наибольшего, или наименьшего, одновременно выборку наибольшего и наиMeift .mero из следующих друг за другом чисел, заданных последовательност ми импульсов, а также определ ть наибольшую разность между ними, Целью изобретени вл етс расширение функциональных возможностей устрой ства за счет осуществлени выборки наибольшего и наименьшего из чисел и определени наибольшей разности между ними. Поставленна цель достигаетс тем, что в устройстве, содержащем счетчики, р1еверсиБный счетчик, схемы сравнени , триггеры, группы элементов И, дейаифра- торы, элементы ИЛИ, элемент НЕ, элементы И, элементы задержки, причем перва шина управлени соединена с первым входом первого дешифратора, втора шина управлени подключена к первому управл ющему входу реверсивного счетчи ка и к первому входу второго дешифрато ра, треть шина управлени соединена с первым входом третьего деши ч атора и. со вторым управл ющим входом реверсив ного счетчика, выходы которого соедйне йы с первыми группами входов первой и второй схем сравнени , со входами эл мента ИЛИ и с информационнымrf входами элементов И первой группы, четверта шина управлени подключена к первому входу четвертого дешифратора и ко второму входу первого дешифратора, выход которого соединен с информационным входом реверсивного счетчики, со вторым входом второго дешифратора и со вторым входом третьего дешифратора информационный вход устройства подключен ко второму входу четвертого дешифратора , к третьему входу первого дешиф ратора и к первому входу первого элемента И, выход которого соединен с третьим входом третьего дешифратора и с информационным входом первого счет3 чика, выходы которого подключены ко второй группе входов второй схемы сравнени , выход которой соединен с четвертым входом третьего дешифратора, п та шина управлени подключена ко второму входу первого элемента И, к п тому входу третьего дешифратора, к первому входу п того дешифратора, к четвертому входу первого дешифратора, к первым управл ющим входам элементов И второй группы и к третьему входу четвертого де- . шифратора, выход которого соединен с информационным входом второго счетчика , выходы которого подключены ко второй группе входов первой схемы сравнени и к информационным входам элементов И второй группы, выходы которых соединены с установочными входами реверсивного счетчика, в отличие от прототипа шеста шина управлени соединена с п тым входом первого дешифратора, с шестым входом третьего дешифратора, со вторым входом, п того дешифратора и с первым входом шестого дешифратора, выход которого подключен к управл ющим входам элементов И первой группы, выходы которых соединены с установочными входами первого счетчика, седьма шина управлени подключена к первому входу второго элемента ИЛИ, выход которого соединен с первыми входами элементов И третьей группы шина сброса подключена ко второму входу второго элемента ИЛИ, ко второму входу шестого дешифратора, к первому входу второго элемента И и черкез первый элемент задержки к третьему входу шестого дешифратора и ко входу второго элемента задержки, выход которого соединен со входом установки в единичное состо ние первого триггера, пр мой выход которого подключен к третьему вхОду первого элемента И и к третьему входу п того дешифратора, инверсный выход , первого триггера соединен с четвертым входом шестого дешифратора, перва шина управлени . подключена ко вторым входам элементов И третьей группы и к седьмому входу третьего дешифратора, первый и второй выходы которого соеди- нены со входами установки в единичное и нулевое состо ние соответственно второго триггера, пр мой выход которого подключен к четвертому входу п того дешифратора и к третьим входам элементов И третьей группы, инверсный выход второго триггера соединен с четвертыми входами элементов И третьей групьпы и с п тым входом п того дешифратора , выход которого подключен к п тому входу шестого дешифратора и ко второму вкоду второго элемента И, выход которого соединен с входом управлени первого счетчика, выход второго элемента задержки подключен к восьмому вкоду третьего дешифратора, к третьему входу второго дешифратора, ко входу управлени реверсивного счетчика и через третий элемент задержки ко вторым управл ющим входам элементов И второй группы, выход первой схемы сравнени соединен с четвертым входом четвертого дешифратора и с четвертым входом второго дешифратора, первый и второй выходы которого подключены ко входам установки в нулевое и единичное состо ни соответственно третьего триггера, пр мой и инверсный выходы которого соединены с п тыми и шестыми входами . элементов И третьей группы, соответственно выход первого элемента ИЛИ подключен к шестому входу первого дешифратора и через элемент НЕ к п тому входу четвертого дешифратора и к четвертому входу первого элемента И.The invention relates to the field of photography and computing and can be used in the development of technical means of digital information control and processing systems. A device for comparing numbers is known, containing registers, triggers, a comparison circuit, logic gates AND, OR, delay elements fll. This device can determine the largest or smallest of consecutive numbers given by pulse sequences. However, the device cannot simultaneously sample the largest and smallest of these numbers, determine the difference between them, and also allow tolerance control over the continuous process or the numbers specified by the pulse sequences. The closest to the proposed by. The technical entity is a device that contains the first and second registers with a summing counting input, a reversible counter (comparison circuits, triggers, AND groups, decoders, AND logic gates, NOT delay elements, in which the outputs of the first register bits are connected to the inputs of the first comparison circuit and with the inputs of the corresponding bits of the reversible counter through the first group of elements I, the other inputs of which are connected through the first delay element to the reset bus of the reversible counter, the outputs of the bits to which are connected to the second inputs of the first and second comparison circuits, to the outputs of the first OR element, the output of which is connected to the input of the NOT element, and to the inputs of the corresponding bits of the second register through the second group of elements And the outputs of the second register bits are connected to the inputs of the second comparison circuit, the first control bus and the reset bus are connected via the second OR element to the first inputs of the third group of AND elements, and the reset bus 3 is connected via the second delay element to the input of the third delay element, forward and the inverse outputs of the first and second triggers are connected to the corresponding inputs of the third group of elements AND 2. In this device, the outputs of the comparison circuits are connected to the counting inputs of two triggers, and the information input of the device is connected to the counting input of the reversible counter. A disadvantage of this device is that it cannot sample the largest, or smallest, simultaneously, the largest and mostMeift .mero from successive numbers given by pulse sequences, and also determine the largest difference between them. It extends the functionality of the device by sampling the largest and smallest of the numbers and determining the largest difference between them. The goal is achieved by the fact that in a device containing counters, a reversible counter, comparison circuits, triggers, groups of AND elements, validators, OR elements, NOT elements, AND elements, delay elements, the first control bus being connected to the first input of the first decoder The second control bus is connected to the first control input of the reversing counter and to the first input of the second decoder, the third control bus is connected to the first input of the third clock on the controller. with the second control input of the reversible counter, the outputs of which are connected with the first groups of inputs of the first and second comparison circuits, with the inputs of the OR element and with the information inputs of the elements of the first group, the fourth control bus is connected to the first input of the fourth decoder and to the second input the first decoder, the output of which is connected to the information input of the reversible counters, with the second input of the second decoder and with the second input of the third decoder information input device connected to the second input at the fourth decoder, to the third input of the first decoder and to the first input of the first element And whose output is connected to the third input of the third decoder and to the information input of the first counter, the outputs of which are connected to the second group of inputs of the second comparison circuit, the output of which is connected to the fourth the input of the third decoder, pin of the control bus is connected to the second input of the first element I, to the fifth input of the third decoder, to the first input of the fifth decoder, to the fourth input of the first decoder, to the first m control inputs of the elements of the second group and the third input of the fourth de. the encoder, the output of which is connected to the information input of the second counter, the outputs of which are connected to the second group of inputs of the first comparison circuit and to the information inputs of the elements AND of the second group whose outputs are connected to the installation inputs of the reversible counter, in contrast to the prototype pole of the control bus is connected to fifth the input of the first decoder, with the sixth input of the third decoder, with the second input, the fifth decoder and the first input of the sixth decoder, the output of which is connected to the control inputs of the element in the first group, the outputs of which are connected to the installation inputs of the first counter, the seventh control bus is connected to the first input of the second OR element, the output of which is connected to the first inputs of the AND elements of the third group, the reset bus is connected to the second input of the second OR element, to the second input of the sixth decoder , to the first input of the second element And and Circassian first delay element to the third input of the sixth decoder and to the input of the second delay element, the output of which is connected to the input of the installation in the unit state ervogo flop, a direct output of which is connected to the third input of the first AND gate and to the third input of the fifth decoder, the inverse output of the first flip-flop is coupled to a fourth input of the sixth decoder, a first control bus. connected to the second inputs of elements of the third group and to the seventh input of the third decoder, the first and second outputs of which are connected to the installation inputs to the single and zero state, respectively, of the second trigger, the direct output of which is connected to the fourth input of the fifth decoder and to the third the inputs of the elements of the third group, the inverse output of the second trigger is connected to the fourth inputs of the elements of the third group and to the fifth input of the fifth decoder, the output of which is connected to the fifth input of the sixth decoder and to The code of the second element And whose output is connected to the control input of the first counter, the output of the second delay element is connected to the eighth video of the third decoder, to the third input of the second decoder, to the control input of the reversible counter and through the third delay element to the second control inputs of the elements And the second group, the output of the first comparison circuit is connected to the fourth input of the fourth decoder and to the fourth input of the second decoder, the first and second outputs of which are connected to the installation inputs to zero and the single states of the third trigger, respectively, the direct and inverse outputs of which are connected to the fifth and sixth inputs. elements of the third group, respectively, the output of the first element OR is connected to the sixth input of the first decoder and through the element NOT to the fifth input of the fourth decoder and to the fourth input of the first element I.

блок-схема устройства приведена на чертеже.block diagram of the device shown in the drawing.

Устройство содержит счетчики 1,2, реверсивный счетчик 3, схемы сравнени 4,5, триггеры 6-8, группы элементов И 9 - 11, дешифраторы 12 - 17 элементы ИЛИ 18, 19, элемент НЕ 20, элементы И 21, 22, элементы задержки 23 - 25,. шины управлени 26 - 30, шину сброса 31, информационный вход 32, выходные шины 33 - 35, шины управлени 36, 37.The device contains counters 1,2, reversible counter 3, comparison circuits 4.5, triggers 6-8, groups of elements AND 9-11, decoders 12-17 elements OR 18, 19, element 20, elements 21, 22, elements delays 23 - 25 ,. control buses 26-30, reset bus 31, information input 32, output buses 33-35, control buses 36, 37.

Устройство работает следующим образом . В.исходном состо нии счетчики 1,2 реверсивный счетчик 3 свободны и триг- Геры 6,8 - в нулевом состо нии. При этом на выходе элемента ИЛИ 18 будет нулевой потенциал, а на выходах элемен- та НЕ 2О и схем сравнени 4, 5 будут единичные потенциалы, причем единичный потенциал на выходе схемы сравнени 5 установит через дешифратор 16 триггер 7 в единичное состо ние.The device works as follows. In the initial state, counters 1.2 reversible counter 3 are free and triggers 6.8 are in the zero state. At the same time, the output of the element OR 18 will be zero potential, and the outputs of the element HE 2O and comparison circuits 4, 5 will have unit potentials, and the unit potential at the output of the comparison circuit 5 will install trigger 7 via the decoder 16 into a single state.

Пусть на шине управлени 27 будет единичный потенциал выборки наибольшего из следующих друг за другом чисел и реверсивный счетчик 3 работает на сложение.Let the control bus 27 be the unit potential of the largest of the consecutive numbers and the reversible counter 3 works on addition.

Первое число, поступившее на информационный вход 32, запишетс через дешифратор 13 в реверсивный счетчик 3The first number received at information input 32 will be written through the decoder 13 into the reversible counter 3

и через дешифратор 12 - в счетчик 1, так как при одинаковых числах в счетчике 1 и в реверсивном счетчико 3 есть единичный потенциал на выходе схемы сравнени 4. Сигнал сброса, поступающий после первого числа на входную шину 31, через элементы задержки 24, 25 стирает содержимое реверсивного счетчика 3.and through the decoder 12 to counter 1, since with the same numbers in counter 1 and in the reverse counter 3 there is a single potential at the output of the comparison circuit 4. The reset signal received after the first number on the input bus 31, through delay elements 24, 25 erases the contents of the reversible counter 3.

Второе число, поступающее на информационный вход 32 устройства также записываетс через дешифратор 13 в реверсивный счетчик 3.The second number arriving at the information input 32 of the device is also written through the decoder 13 to the reversible counter 3.

Если второе двоичное число окажетс больше первого двоичного числа, записанного в счетчике 1, то на выходе схемы сравнени 4 в момент равенства чисел в счетчике 1 и в реверсивном счетчике. 3 по вл етс единичньгй сигнал и осталные импульсы второго числа также поступают через дешифратор 12 на вход счетчика 1.If the second binary number is greater than the first binary number recorded in counter 1, then the output of the comparison circuit 4 at the time of equality of the numbers in counter 1 and in the reversible counter. 3, a single signal appears and the remaining pulses of the second number also arrive through the decoder 12 to the input of counter 1.

В случае, если второе двоичное число меньше или равно первому двоичному числу, то содержимое счетчика 1 останес без изменений. ;.If the second binary number is less than or equal to the first binary number, then the contents of counter 1 remain unchanged. ;.

Сигнал сброса, поступающий после второго числа на вкодную ш.ину 31,.чирез элементы задержки 24, 25 стирает содержимое реверсивного счетчика 3.The reset signal, arriving after the second number on the code line 31,. Delay elements 24, 25 erases the contents of the reversible counter 3.

При поступлении на информационный вход 32 устройства следующего сравниваемого числа операции сравнени производитс аналогично описанному и результат сравнени всегда оказываетс записанным в счетчике 1.When the next comparative operation number is compared to the information input 32 of the device, the comparison is performed in the same way as described, and the result of the comparison is always recorded in counter 1.

В результате в счетчике 1 будет наибольшее из следующих одно за другим чисел, заданных последовательност ми импульсов,,As a result, in counter 1 there will be the greatest of the numbers following one after the other, given by sequences of pulses,

Пусть, например, на шине управлени 29 будет единичный потенциал выборки наименьшего из. следующих друг за другом чисел и реверсивный счетчик 3 работает на сложение.Let, for example, on the control bus 29 be the unit potential of the smallest sample. consecutive numbers and the reversible counter 3 works on addition.

Claims

The first number arriving at information input 32 will be written through the decoder 13 into the reversible counter 3. The reset signal received after the first number on the bus 31 through the decoder 14 will overwrite. the contents of the reversible counter 3 in the counter 2 and through the delay elements 24, 25 erase the contents of the reversible counter 3 and sets the trigger 8 to the one state, and then through the decoder 16 sets the trigger 7 to the zero state. i If the first number is zero, after the termination of the reset signal at the output of the comparison circuit 5 there will be a single signal that will set the trigger 7 in the one state. The second number arriving at information input 32 is also recorded in reversible counter 3. If the first number is zero, then. the reset signal, arriving after the second number on the input bus 31, through the delay elements 24, 25 erases the contents of the reversible counter 3. After termination of the reset signal, trigger 7 will be in one state. If the first number is not zero, then when the second number arrives at information input 32, a single signal appears at the output of comparison circuit 5 at the moment of equality of the numbers in counter 2 and in reversing counter 3, which through the decoder 16 sets the trigger 7 in a single state. The reset signal arriving after the second number on the input bus 31,. through the delay elements 24, 25 collects the contents of the up-down counter 3 and further through the decoder 16 sets the trigger 7 to the zero state. If the first number is not equal to zero, and after the arrival of the second number at information input 32, trigger 7 in the null state, the reset signal, coming after the second number, to the input bus 31 through AND 22 erases the contents of counter 2 through delay element 24 and The decoder 14 will overwrite the contents of the reversible counter 3 into the counter 2 and further, through the delay element 25, erases the contents of the reversible counter. When the next compared number is compared to the information output Device 32, the comparison operation is It is as described, and comparing the results tat It appears always recorded in the counter 2. As a result, in counter 2 there will be the smallest of the numbers following one after the other, given by sequences of pulses. If it is necessary to simultaneously determine the largest and smallest of the consecutive numbers on the control tires 27 and 29, there should be unit potentials. In this case, the device works in a similar way. As a result, counter 1 will have the largest, and counter 2 will have the smallest of the numbers following one after the other given by the sequences of pulses. Let control bus 28 be a single signal of simultaneous sampling of the largest of the consecutive numbers and the largest difference between these numbers. In this case, the reversible counter 3 works on subtraction. The first number arriving at information input 32 will be written through the decoder. 12 to counter 1, since the J output of the element is NOT 2O is the unit potential, and the reset signal, which arrives after the first number on the reset bus 31, sets the trigger 8 via the delay elements 24, 25, and the trigger 7 via unit decoder 16 then through delay element 24 will overwrite the contents of counter 1 into reversible counter 3. If the first number is zero, then the second number arriving at information input 32 will be written through the decoder 12 into counter 1 and through the element 21 into counter 2. Etc. and this, the signal from the output of the element 21 sets the trigger 7 to the zero state via the decoder 16. Reset signal arriving The second isla is connected to the reset bus 31, delays the contents of counter 1 into the reversible counter 3 via delay elements 24, 25 and 23, and also sets the trigger 7 to the one state via the decoder 16. If the first number is not zero, then the second number will flow through the decoder 13 to the counting input of the reversible counter 3, reducing it. content. If the second number is equal to or less than the first, then the trigger 7 will be in one state and the reset signal, coming after the second number on the input bus 31, will erase the contents of counter 2 through the AND 22 element and will rewrite the decoder 14 through the delay element 24. The contents of the reversible counter 3 in the counter 2, and then through the delay element 25 erases the contents of the reverse counter 3 and through the element. delay 23 overwrites the contents of counter 1 to reversible counter 3. If the second number is larger than the first, when the second number arrives at the information code 32, when the contents of the reversing counter 3 is zero, a single signal appears at the output of the element HE 20 and the remaining pulses of the second number arrive at the summing counting the input of the counter 1, as well as through the element 21 to the summing input of the counter 2. In this sig. The gate from the pickup of the element 21 sets the trigger 7 to the zero state via the decoder 16. If the second number is greater than the first, then the reset signal, arriving after the second number on the input bus 31, through delay elements 24, 25 and decoder 16 sets trigger 7 to one state and through delay element 23 rewrites the contents of counter 1 to reversible counter 3. As a result, in counter 1 there will be more of the two numbers given by successive pulses, and in counter 2, the difference between these numbers. If a. the number in the reversible counter 3 is not equal to zero, then the third number will go through the decoder 13 to the counting input of the reversible counter 3, its contents will be reduced. If the number in the counter 2, for example, is not zero, then upon receipt one third of its number at information input 32 at the moment of equality of the numbers in counter 2 and in the reversible counter 3 at the output of the comparison circuit 5 there will be a unit potential. If, after the appearance of a single potential at the output of the comparison circuit 5, the pulses of the third number are further fed to the information input 32, then the first pulse at the input 32 after equality of the numbers in the reversible counter 3 and the counter 2 sets the trigger 7 to zero via the reverse decoder 13 and 16 condition. If the third number is larger than the first two numbers, then at the moment when the contents of the reversing counter 3 is zero, a unit potential appears at the output of the element HE 20, and the remaining pulses of the third number arrive through the decoder 12 at the information input of the counter 1 as well as through the element AND 21 of the input of the counter 2. The reset signal, arriving after the third day on the bus 31, overwrites the contents of counter 3 into the counter. 2, the contents of counter 1 in the reversible counter 3 and sets the trigger 7 to one state similar to the reset signal after the second number. When the next compared number is received at information input 32, a comparison operation is performed in the same way as described. As a result, counter 1 will have the largest of the numbers following one after the other, given by sequences of pulses, and counter 2 will have the largest difference between these numbers. In the case of comparing the numbers given by the pulse sequences with the limits of the measured numbers recorded in counters 1 and 2, the control buses 26 and 30 must have zero and unit potentials, respectively. The first number arriving at the information input 32 via the decoder 13 will be recorded in the reversible counter 3, working on addition. If the first number is less than the lower limit of the measured numbers recorded in register 2, then when a reset signal arrives after the number on the input bus 31, there will be a signal on the output bus 34 indicating that the number recorded in the reversible counter 3 is less than the lower predal of the measured numbers. If the first number is less than the upper limit recorded from counter 1, but greater than the lower limit of the measured numbers recorded in counter 2, then at the moment of equality of numbers in the reverse counter 3 and in counter 2, the output of the comparison circuit 5 will be a signal through the decoder 16 flips trigger 7 into one state. When a reset signal is received after the number on the input bus 31 on the output bus 33, there will be a signal indicating that the number recorded in the reversing counter 3 is within the measured numbers. If the first number is greater than the upper limit of the measured numbers recorded in counter 1, then at the moment of equality of the numbers recorded in the reversible counter 3 and the lower limit of the measured numbers of counter 2 and in the reverse counter 3 and the upper limit of the measured numbers of counter 1, at the outputs The corresponding comparison schemes 4, 5 will be single signals. The single signal at the output of the comparison circuit 5 through the decoder 16 sets the trigger 7 to the single state. If at the output of the comparison circuit 4 there is a unit potential and the next impulse arrives at the counting INPUT of the reversible counter 3, then this impulse through the decoder 15 sets the trigger 6 in the unit state. When a reset signal is received after the first number on the input bus 31 on the output bus 35, there will be a signal indicating that the number recorded in the reversible counter 3 is greater than the upper limit of the measured numbers. Moreover, the reset signal through the delay elements 24, 25 and through the decoders 16, 15 always sets the triggers 6, 7 to the zero state. When the next compared number is received at the information input of the device 32, a comparison operation is performed similarly. In the case of a comparison of a continuous process given by pulsed investigations with the limits of measured values. villages recorded in counters 1, 2, on the control and 26 buses, the AO must have single potentials. The pulses arriving at Ttn the input input 32 through the decoder 13 are passed to the counting input of the reversing counter 3, which operates depending on the nature of the process of repetition or subtraction. In every minute. time in the reverse counter 3 will be a number characterizing the process. Let, for example, the reversible counter 3 is free and the instantaneous value of the magnitude of the continuous process increases. In this case, the reversive counter 3 works on addition, and on the output bus 34 there will be a signal indicating that the instantaneous value of the junction in the intermittent process is less than the bottom: the number of measured numbers. At the moment of equality of the numbers in the reversible counter 3 and the lower limit of the measured numbers of the counter 2, the output of the comparison circuit 5 will be a signal that through the decoder 16 will transfer the trigger 7 to a single state and on the output bus 33 will turn on the signal indicating that the instantaneous value of the continuous process is within the limits of the measured numbers. . . . In case after switching the trigger 7 to the single state; If the value of the continuous process starts to decrease, then the reversible counter 3 in this case will work for subtraction. With a single signal at the output of the comparison circuit 5, the first pulse at the counting input of the reversible counter 3 will return the trigger 7 to the zero state via the decoder 16, as a result of which the output bus 34 again receives a signal. If, after the flip-flop of the trigger 7 to the one state, the instantaneous value of the continuous process value further increases (the reversible counter 3 works on addition), then the trigger 7 will not change its state. Wherein . the output of the comparison circuit 5 will be a zero signal. If after this the instantaneous value of the continuous process decreases (the reversible counter 3 works on subtraction), then at the moment of equality of the numbers in the reversible counter 3 and the lower limit of the measured numbers of the counter 2, a single potential appears at the output of the comparison circuit 5. In case the trigger 7 is in the unit state and the instantaneous value of the continuous process increases (the reversible counter 3 works on addition), then at the moment of equality of the numbers in the reversible sychatchik 3 and the upper limit of the number of counts. The tick 1 at the output of the comparison circuit 4 will be a single signal. . If at the output of the comparison circuit a single signal and the instantaneous value of the continuous process increases further, then with a single signal at the output of the comparison circuit, the first impulse at the counting input of the reversible counter 3 through the decoder 15 sets the trigger 6 into a single state, as a result of which Wits signal indicating that the instantaneous value of the value of the continuous p | eocess is greater than the upper limit of the measured numbers. At the same time, a zero signal is set at the output of the comparison circuit 4. If, after the flip-flop of the trigger 6B, the unit state, the instantaneous value of the continuous process increases further, then the trigger 6 does not change its state, and the output of the comparison circuit 4 will be a zero signal, and a single signal on the output bus 35. . In case, after this, the instantaneous value of the quantity. Continuous process is reduced (reversible counter 3 works on subtraction), then at the moment of equality of numbers in the reversing counter 3 and the upper limit. measurable. the numbers of the counter 2 pa output circuit comparison 4 will be a single signal, which, after 137, the decoder 15 will return the trigger 6 in the zero state, resulting in a single signal on the output bus 33, indicating that the instantaneous value of the continuous process within the measured numbers. As a result, at one of the outputs 33, 34, 35 of the device there will be a signal characterizing the current process at a given time. The device can sample the largest or smallest, simultaneously the largest and smallest of successive numbers given by the pulse sequences, as well as a sample of the largest of the successive numbers while simultaneously determining the largest difference between them. In addition, the device may carry out a tolerance control of the continuous process or the numbers specified by the pulse sequences. DETAILED DESCRIPTION OF THE INVENTION A device for comparing numbers containing counters, a reversible counter Comparison Schemes. Triggers, AND groups, decoders, OR elements, NOT elements, AND elements, delay elements, the first control bus connected to the first input of the first decoder, the second control bus connected to the first control input of the reversible counter and to the first input of the second decoder, a third the control bus is connected to the first input of the third decoder and to the second control input of the reversible counter, the outputs of which are connected to the first groups. and mi inputs of the first and second circuits compared. . nor, with the inputs of the first OR element and with the information inputs of the AND elements of the first group, the fourth control bus is connected to the first input of the fourth decoder and to the second input of the first decoder, the output of which is connected to the information input of the reversible counter, with the second input of the second decoder and with the second the input of the third decoder, the information input of the device is connected to the second input of the fourth decoder, to the third input of the first decoder and to the first input of the first And element; the output of which is connected to the third input 3 of the third decoder and informational; the input of the first counter 1a, the outputs of which are connected to the second group of inputs of the second comparison circuit, the output of which is connected to the fourth input of the third decoder; the pin of the control bus is connected to the second input of the first element AND, to the fifth input of the third decoder; . to the fourth input of the first decoder, to the first control inputs of the elements of the second group and to the third input of the fourth decoder, the output of which is connected to the information input of the second counter, the outputs of which are connected to the second group of inputs of the first comparison circuit Groups whose outputs are connected to installation inputs (reversible counter, characterized in that, in order to extend the functionality by sampling the largest and smallest numbers and determine the largest difference between them; in it, the control bus is connected to the fifth input of the first decoder, to the sixth input of the third decoder, to the second input of the fifth decoder and to the first input of the sixth decoder, the output of which is connected to the control inputs of the AND first elements the groups whose outputs are connected to the installation inputs of the first counter, the seventh control bus is connected to the first input of the second OR element, the output of which is connected to the first inputs of the AND elements of the third group, the reset bus Yuechena to the second input of the second element OR, to the second input of the sixth decoder, to the first input of the second element And through the first delay element to the third input of the sixth decoder and to the input of the second delay element, the output of which is connected to the input of the installation in the unit state of the first trigger, the direct output of which is connected to the third input of the first element I and to the third input of the 5th decoder, the inverse output of the first trigger is connected to the fourth input of the sixth decoder, the first control bus is connected to second inputs of the AND of the third group and the third to the seventh input of the decoder, the first and second outputs which are connected to the inputs of a single setting and zero state, respectively the second flip-flop. the direct output of which is connected to the fourth video of the first decoder and to the third inputs of elements of the third group, the inverse output of the second trigger is connected to the fourth inputs of the elements of the third group and the fifth input of the fifth decoder, the output of which is connected to the fifth video the sixth descriptor and to the second input of the second element And, the code of which is connected to the control input of the first counter, the output of the second delay element is connected to the eighth input of the third decoder-, radiator to the third input of the second decoder, to the input y control of the reversible counter and through the third delay element to the second control inputs of the AND elements of the second group, the output of the first comparison circuit is connected to the fourth, the input of the fourth decoder and 316 to the fourth input of the second decoder, the first and second outputs of which are connected to the inputs of the unit to zero and one the states of the third trigger, respectively, the direct and inverse outputs of which are connected to the fifth and sixth inputs of the AND elements of the third group, respectively, the output of the first. element OR is connected to the sixth input of the first decoder and through the element NOT to the fifth input of the fourth decoder and to the fourth input of the first element I. Sources of information taken into account during the examination 1. USSR Author's Certificate number 466508 Cl. G 06 F 7/04, 1973.

2.Avtorskoe, certificate of the USSR No. 487385, cl. Q About F 7/04, 1973 (prototype) ..