SU750480A1 - Device for comparing numbers with tolerances - Google Patents

Description

(54) DEVICE FOR COMPARING NUMBERS

one

The invention relates to automation and computing and can be used in automated digital monitoring and control systems.

Devices are known for comparing numbers with tolerances for testing the performance of a control object on the principle of “less,” rate, “more with a split tolerance field into grades 1.

The disadvantage of the device is that it has a significant error of the comparison result in gradations, which is caused by the rounding of the gradation value to an integer.

The closest to the proposed technical entity is a device containing AND, AND-OR-NOT elements, a trigger, counters, a reversible counter, comparison circuits, a memory block, the first control input of the device connected to the first input of the first, second and third elements And, by the first control input of the reversible counter and with the control input of the memory unit, the outputs of which are connected to the first input groups of the first and second comparison circuit, the second input groups With ACCESS

which are connected to the outputs of the first counter and the reversible counter, respectively, the second input of the first element I is connected to the second control input of the device, and the output is informational (counting)

5 to the input of the reversible counter and the first counter, the output of the first comparison circuit is connected to the control inputs of the first counter and to the information input of the second counter, the outputs of which are connected to the inputs of the And group elements, the first output

10 of the second comparison circuit is connected to the first input of the AND-OR-NOT element and to the second input of the second element AND, the second output of the comparison circuit is connected to the second input of the AND-OR-NOT element and to the second

j to the input of the third element AND, the outputs of the second and third elements AND are connected to the inputs of the trigger installation in the single and zero state respectively, the direct output of the trigger is connected to the third input of the AND-OR-NOT elements and to the second input

20 of the control of the reversible counter, the inverse output of the trigger is connected to the fourth input of the AND-OR-NOT element and the third control input of the reversible counter, the output of the AND-OR-NOT element is connected to the control inputs of the ANDF group's third input and to the third input of the first And 2 element. The drawback of the device is that when rounding the code of the value of one gradation to an integer, the accuracy of the comparison result depends on the degree of rounding and the amount of deviation of the code of the value of the measured parameter from its nominal value. The purpose of the invention is to improve the accuracy of comparing numbers with tolerances when splitting the tolerance field into gradations. The goal is achieved by the fact that a device containing groups of elements AND, elements AND, a trigger, counters, a reversible counter, comparison circuits, a memory block, the first control input of the device connected to the first inputs of the first, second and third elements AND control of the reversible counter and with the control input of the memory unit, the first and second groups of outputs of which are connected to the first groups of inputs of the first and second comparison circuits, respectively, the second group of inputs of the first comparison circuit connected to the output Dami reversible counter, the second group of inputs of the second comparison circuit is connected to the outputs of the first counter, the second input of the first element I is connected to the second control input of the device, and the output of the first element I is connected to the information input of the first counter, the output of the second comparison circuit is connected to the control input of the first the counter and the information input of the second counter, the outputs of which are connected to the inputs of the elements AND of the group, the first and second outputs of the first comparison circuit are connected to the first inputs of the second and third elements And respectively, the output of the second element I is connected to the input of the installation in a single trigger state, the output of the third element I is connected to the input of the installation in a zero state of the trigger, the direct and inverse outputs of which are connected respectively to the second and third control inputs of the reversible counter, the third the output of the first comparison circuit is connected to the control inputs of the AND elements of the group and the third input of the first AND element, the third counter and the third comparison circuit are introduced, the first group of inputs of which is connected the third group of outputs of the memory unit, and the second group of inputs is connected to the outputs of the third counter, the information input of which is connected to the output of the first element I, and the output of the third comparison circuit is connected to the control input of the third counter and to the information input of the reversible counter. The drawing shows the block diagram of the device. The device contains a reversible counter 1, the element And 2, schemes 3, 4, 5 comparison, block 6 memory, counters 7, 8, 9, a group of elements And 10, elements And 11, 12, trigger 13, input bar 14, inputs 15 , 16 control, input bus 17, output buses 18, 19, 20. The device works as follows. Before starting work, the device receives a reset signal (not shown), which sets all three counters to the zero state. Information about the measured value of the parameter in the form of a code, inputted on the input bus 14, is recorded in forward code to the reversible counter 1 by a signal inputted on the control input 15. With the same signal, the first element 2 opens, and codes written on the input bus 17 are also recorded in memory block 6. These codes correspond to the nominal value of the parameter, the value of the tolerance and the number of gradations in the tolerance field. In the comparison circuit, the codes of the nominal value of the parameter coming from the memory block 6 and the measured value of the parameter coming from the reversible counter 1 are compared and the result of the comparison is recorded into trigger 13 by a signal at the control input 15 through elements 11, 12. With the value of the measurement code value less than the nominal value of the parameter; the signal from the first output of the comparison circuit 4 sets the trigger 13 to a position that indicates the sign of the deviation of the measured parameter from its nominal value which in this case is "less, as indicated by the signal on the output bus 19 and switching the reversing counter 1 to the addition mode on the second control input. The sequence of the clock pulses on the input bus 16 through the open element And 2 enters the information input of the counters 7 and 8, operating in the counting mode. The result corresponding to the number of received clock pulses is compared by comparison circuit 3 with the code received from memory block 6, the value of which is equal to the number of gradations into which the tolerance field is divided. The result of comparing the codes in the form of a signal from the output of the comparison circuit 3 is fed to the information input of the reversible counter 1 and to the input of setting the zero state of the counter 7. Thus, in the reversible counter 1, the code value increases by one in one clock cycle of matching the codes in the comparison circuit 3 . This process is repeated periodically until a sequence of clock pulses exists at the information input of counter 7. If the code of the reversible counter 1 is equal to the code of the nominal value received from memory block 6 in the comparison circuit 4, the signal from the first output is removed, and the third output is generated the signal that closes the element 2, stopping the arrival of the clock pulses at the information input of counters 7 and 8. At the same time, the signal from the third output of the comparison circuit 4 is fed to the input of the group e The elements 10, the second input of which receives the counter code 9, and if they coincide, the code corresponding to the gradation enters the output bus 18 of the device.

The code value corresponding to the number of received clock pulses in counter 8 is compared with the code received from memory block 6, the value of which is equal to the tolerance code. The result is compared to these codes in the form of a signal from the output of the comparison circuit 5 to the information input of the counter 9 and to the installation input to the zero state of the counter 8. Thus, for each code tick in the comparison circuit 5, at which the quantity 8 clock pulses equal to the value of the tolerance code, one pulse is sent to the counter 9. This process is repeated periodically until a sequence of clocks exists on the information input of the counter 8.

From the output of the counter 9, information about the number of gradations placed in the deviation of the measured parameter from the nominal is removed.

If the code of the measured parameter value is within the tolerance or beyond the tolerance field, but is greater than the nominal value of the parameter, then the second output of the comparison circuit 4 produces a signal with a logic level "1, and there is no signal at the first and third output, i.e. logical level “O. The signal from the second output of the comparison circuit 4 sets the flip-flop 13 to the position providing the signal output by the level "1 at the output 20, indicating that the code of the measured parameter value is more than the nominal value. At the same time, the signal level "1" from the second output of the comparison circuit 4 switches the reversing counter 1 to the subtraction mode via the third control input. The sequence of clocking pulses, similarly to the previous one, is fed through the open element I 2 to the information input of counters 7 and 8 operating in the counting mode and the value of the codes of these counters are compared by comparison circuits 3 and 5, respectively, from the output of which the result of comparing codes as a signal goes to the input setting the zero state of the counters 7 and 8, respectively, to the information input of the reversible counter 1 and the counter 9. Thus, in the reverse counter 1, for one clock cycle, the codes in the comparison circuit 3 The reading of the code is reduced by one. This process is repeated periodically until the code value in the reversible counter 1 becomes equal to the code of the nominal value of the parameter of the incoming circuit 4 of the comparison from memory block 6. With the equality of the codes in the scheme 4 of the comparison at its third output

The signal is generated by the level "1", which closes the element AND 2, stopping the arrival of clocking pulses at the information input of counters 7 and 8 and opens the group of elements AND 10, providing an indication of the code of the number (value) of gradations recorded by the counter 9. Thus, in this case the amount of deviation of the measured parameter from its nominal value in the gradation and its sign is determined.

0 The introduction of the third counter, the third comparison scheme and the new connections favorably distinguishes the proposed device for comparing numbers with tolerances from the known, as it increases the accuracy of the device. There is no error in the device resulting from rounding the code of the value of one gradation to an integer, since the code of the tolerance field value and the number of the number of gradations are entered into the memory block. Thus, in the proposed device, the code multiplies the value of the deviation of the measured parameter from its nominal value by the number of gradations in the tolerance field while simultaneously dividing the packet of clock pulses by the counter 8 and the comparison circuit 5. Comparison result

is entered into the counter 9.

Claims (2)

1. USSR author's certificate number 543936, cl. G About F 7/04, 30.05.74. 2. USSR author's certificate for application number 2513688, 02/19/78 (prototype).