SU1401448A1 - Apparatus for implementing boolean symmetrical functions - Google Patents

Abstract

The invention relates to a variety of techniques and can be used in systems for the transfer and processing of discrete information. The aim of the invention is to increase speed. The device contains a register 1, a switch block 2, an adder 3, a result formation block 4, a control block 5, information inputs 6, a threshold value input 7 (function values, read gating) of a result formation block 8 reset input 8, a clock input 9, an output 10 signs of the end of calculations, output 11 of the result. The device allows for the implementation of threshold symmetric functions, the elementary symmetrical functions and arbitrary symmetric functions. 3 hp f-ly, 1 ill. With s

Description

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The invention relates to computing and can be used in systems for the transmission and processing of discrete information.

The aim of the invention is to increase the speed.

The drawing shows the functional diagram of the device.

The device contains a register 1, a switch block 2, an adder 3, a result generation block 4, a control block 5, information inputs 6, a threshold value input 7 (function values, read gating) of a result generation unit, a reset input 8, a clock input 9, an output 10 sign of the end of calculations, output 1 1 result.

Control unit

contains, for example

measures, counter 12, first 13 and second 14 elements OR.

The device operates as follows.

Information inputs 6 are supplied with an input code, and device input 8 is supplied with a reset pulse, which sets the control unit counter 12 to the zero state. In this case, the code from the information inputs 6 is fed to the inputs of the adder 3, which performs the summation of the units of the input code, and bits 21 and 2.1-1 of the input code (1 1.2, .. n / 2) are fed to the inputs 2i-1- ro bit of the adder 3. At the same time, the signal at the input 8 of the device allows the code to be written from the outputs of the adder 3 to register i. At the end of the pulse at the input 8 of the device reset, the clock input 9 is supplied to the clock pulses. When the first clock pulse is applied, the block of switches 2 via the signals from the outputs of the counter 12 of the control unit 5 connects to the first discharge inputs of the adder 3 signals from the outputs of the first and third register bits 1, to the inputs of the second digit of the adder - signals from the outputs of the second and fourth bits of the register 1, to the inputs of the fifth and sixth bits of the adder 3 from the outputs of the fifth and seventh bits of the register 1 and from the outputs of the sixth and eighth bits to Register 1 etc As a result, at the outputs of the bits of the adder 3, codes of the sum of the number of units in groups of four bits of the input code are formed. In general, the k-M cycle of the device’s operation

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the inputs of the adder 3 from 2 -jH-ro to 2 j + k + 1-th bit (k 1,2 ..., j 0,1, ..., Jn / 2 -1) respectively, the signals from the outputs of the bit The register register 1 is from + 1-TH to j-fk + 1-th to the inputs of the first term and from (j + 1 + 2) -ro to (,) -th to the inputs of the second term. This is accomplished using a block of 2 switches. As a result, the outputs of the adder 3 sequentially form the sums of the number of units in the groups of input code of four, eight, sixteen, and so on. Codes from the outputs of the adder on X1 each cycle of the device operation are recorded in register 1 and are used as input codes of the adder 3 on the next cycle. As a result, on the last kM cycle (k C -1) at the outputs of the lower log2 (n + 1) t bits of the adder 3, the sum code of the number of units in the input code is generated. In this case, the signal from the output of the counter 12 of the control unit 5 blocks the further operation of the device. The code of the number of units of the input code from the outputs of the digits of the adder 3 is fed to the inputs of the result formation unit 4,

In the case of the implementation of threshold functions, the inputs 7 of the result formation unit 4 are supplied with a code, an additional threshold of the function being implemented.

Block 4 is designed as an adder. In this case, if in the input code the number of units is not less than the threshold, then at the transfer output of the adder, which is in input 11 of the device, there will be a single signal, otherwise - zero,

In the case of the implementation of elementary symmetric functions, the index code of the calculated function is supplied to the inputs of the result generation unit 4. Block 4 is made in the form of a comparison circuit. In this case, if the number of units in the input code is equal to the code applied to inputs 7, then at output 11 of the forming unit 4

the result will be a single signal, otherwise - zero.

In the case of implementing an arbitrary symmetric function (system), the D-formation block is executed as a memory block, the inputs of which from the cjTMMaTopa 3 outputs receive the code of the number of units of the input code, which is the address of the cell in which the output code is written. To input block 7

4, a signal is output from the output 10 of the sign of the end of the calculations of the control unit 5, according to which the result is read and output to output 11,

the reset of which is connected to the same input of the control unit.

2. The device according to claim 1, about t l and the formula of the invention

monotonous (threshold) symmetric functions, the result forming unit contains a threshold adder, and the inputs of the first summand sum are 1. A device for implementing the threshold for the buoyer of the matrix is connected to the inputs

output symmetric functions containing

register, adder and control block.

the block argument, the inputs of the second term of the threshold adder are connected to additional inputs of the device threshold value, the overflow output of the threshold adder is connected to the output of the result formation unit,

characterized in that.

the block argument, the inputs of the second term of the threshold adder are connected to additional inputs of the device threshold value, the overflow output of the threshold adder is connected to the output of the result formation unit,

3. The device according to claim 1, characterized in that when calculating elementary symmetric functions in order to improve speed, the switchgear unit and the result formation unit are additionally introduced into it, and the information inputs of the first and second groups of the switch unit are connected to the outputs of the corresponding bits the register and the information forming the result of the joint inputs of the device correspond to the comparison circuit, the input is the first wave, the control inputs of the switch operand of which are connected to the input of the unit are connected with the outputs of the argument number. block, the input of the second one-; The pa of the control unit clock, the first of the comparison circuit, is connected to the output group of the commutator of the block; 25 Additional input of the function is functioned with the input of the first term, the output is the sign of equality of the comparator, the second group of room outputs is connected to the output of the forumulator block block is connected to the input of the world result. The second term of the adder, the outputs of the adder are connected to the inputs of the argument of the result generation block and the information inputs of the register, the clock input of which is connected by the d clock output of the control block

4, The device according to claim 1, which is based on the fact that when calculating arbitrary symmetric functions, the result formation unit contains a memory block, the address inputs of which are connected to the block argument input, the read gating input of the memory block the end of the calculation of the control unit, the output of the memory unit is connected to the output of the result generation unit.

with the same input of the device, the output of the sign of the end of the calculations of the device is connected to the same output of the control unit, the output of the result generation unit is the output of the result of the device, the input

the reset of which is connected to the same input of the control unit.

2. The device according to claim 1, about tl and the block argument, the inputs of the second term of the threshold adder are connected to the additional inputs of the device threshold value, the overflow output of the threshold adder is connected to the output of the result formation unit,

3. The device according to claim 1, characterized in that when calculating elementary symmetric functions

 ° result formation contains a comparison circuit, the input of the first operand of which is connected to the input of the argument, the block, the input of the second one of the comparison circuit is connected to the Auxiliary input of the function value, the output of the equal comparison indicator is connected to the output of the result formation block .

15 0 ° of the formation of the result contains a comparison circuit, the input of the first operand of which is connected to the input of the argument, the block, the input of the second one-; The comparison circuit's rand is connected to the 25 Additional input of the function magnitude, the output of the equality of the comparison indicator is connected to the output of the result formation block.

0

five

0

4, The device according to claim 1, which is based on the fact that when calculating arbitrary symmetric functions, the result formation unit contains a memory block, the address inputs of which are connected to the block argument input, the read gating input of the memory block the end of the calculation of the control unit, the output of the memory unit is connected to the output of the result generation unit.

Claims (4)

Claim 1. A device for implementing Boolean symmetric functions, comprising a register, an adder and a control unit, characterized in that, in order to improve performance, it additionally includes a block of 15 switches and a block for generating the result, the information inputs of the first and second groups of the switch block are connected to the outputs of the corresponding bits of the register and information inputs of the device, respectively, the control inputs of the switches of the block are connected to the outputs of the clock number of the control block, the first group is the output in the block switch, 25 is connected to the input of the first term adder, the second group of outputs of the block switches is connected to the input of the second term adder, the outputs of the adder are connected to the argument inputs of the result formation block and the information inputs of the register, the synchronizing input of which is connected by the clock output of the control unit whose clock input is connected to the device input of the same name, the output of the sign of the end of the device calculations is connected to the control unit output of the same name, the output of the The result is the result of the device, the reset input of which is connected to the input of the control unit of the same name. 2. The device according to claim 1, characterized in that. When calculating monotone (threshold) symmetric functions, the result generating unit contains a threshold adder, the inputs of the first term adder of the threshold being connected to the inputs of the argument block, the inputs of the second term of the threshold adder being connected to additional inputs the threshold value of the device, the overflow output of the threshold adder is connected to the output of the result formation unit, 3. The device according to claim 1, characterized in that when calculating the elementary symmetric functions, the result generating unit contains a comparison circuit, the input of the first operand of which is connected to the input of the argument. Block, the input of the second operand of the comparison circuit is connected to an additional input of the function. tion, the output of the sign of equality of comparison is connected to the output of the result formation unit. 4. The device according to claim 1, characterized in that when calculating arbitrary symmetric functions, the result generating unit contains a memory block, the address inputs of which are connected to the input of the block argument, the input gate of the reading of the memory block is connected to the output of the sign of the end of the calculation of the control unit, the output of the block memory is connected to the output of the block forming the result.