SU1661791A1 - Boolean differential equations solving device - Google Patents

Abstract

The invention relates to digital computing and can be used as hardware support for computing in computer-aided design systems for digital automata, in analyzing and diagnosing combinational circuits, in logic control systems for robotic manipulators, and flexible automated productions. The purpose of the invention is to expand the functionality by solving Boolean differential equations. The goal is achieved by the fact that the device contains 2 ^N control blocks 1, where N is the number of Boolean variables, 2 ^N blocks 2 decryption, 2 ^N computing blocks 3 and switch 4. The initial Boolean differential equation, represented as a system of Boolean equations in the form of Zhegalkin is solved by means of the fast discrete Fourier transform in the conjunctive basis. 4 il.

Description

sc

Os

3

Lnf 8/00

The invention relates to digital computing and can be used as hardware support for computing in computer-aided design systems for digital automata, in analyzing and diagnosing combinational circuits, in logic control systems for robotic manipulators, and flexible automated productions.

The purpose of the invention is to expand the functional capabilities by solving Boolean differential equations,

The device (Fig. 1) contains 2 control blocks 1, 2P decryption blocks 2, 2P computing blocks 3 and switch 4. Each control block 1 (Fig. 2) contains the first 5 and second 6 triggers and element 7. Each decryption block 2 (Fig. 3) contains a decoder 8, registers 9, elements AND 10 of the first group, elements 11 of the second group and an element OR 12. Each computing unit 3 (Fig. 4) contains an adder 13 modulo two, elements AND 14 shifting the registers 15, the first 16 and second 17 OR elements and the delay element 18.

The device has the following operation algorithm.

At the first stage, a truncated discrete Fourier transform is performed in the conjunctive basis according to the matrix relation:

X K22nF2n (mod2),

() where F2ri is the differentiation matrix

dimension 2пх2п, formed by the ratio

$ - |,) T

F

eleven

 ® 2

  1, n,

where I 21 1 and 12P are the unit matrices of dimensions 2mx2 1 and 2gHx2 | respectively

 - the symbol of the Kronecker matrix product, and when multiplying

. (ABOUT-

the matrices F 2 and the vectors X are used for the conjunction and modulo two summation operations.

The matrix K 22 of dimension 22 x2 is formed from the matrix of conjunctive pre "According to the EP

forming a K22 of dimension 2 x 2 by highlighting columns 2 (, 2n-1) and deleting the rest:

K2 K2 -1 ЈK2;

 1 o 1 1

M, 2P, K2

0

5 0 5

0

five

0

five

0

five

At the second stage, the X ™ vectors of the system X are executed with the operation of elementwise disjunction. As a result, the solution vector G is obtained (as a result of combining the solutions of the individual equations of the system).

At the third stage of the algorithm, the zero elements of the decision vector are determined whether the corresponding sets of variables

x (o) d (1) x2 1, which are the coefficients of the value vectors

(1 ... h2P-1 t

the desired Boolean functions f (X).

The operation of the 1st control block 1 (, 2P) is considered on the example of the control block 11.

At the moment of time to the counting input of the trigger 5, a clock pulse arrives and the output of the trigger 5 forms the logic level O. It is transmitted from the output of the trigger 5 to the first input of the And 7 element and to the third output of the block 11. At the moment of time to the input of the installation to 1 trigger 6 receives a high logical signal level and the output of trigger 6 generates a logic level 1, which is transmitted to the second output of the IL block. A high level signal is fed to the second input of an And 7 element, from whose output a low logic level is transmitted to four th output unit 1i.

At time t, a clock pulse arrives at the counting input of the trigger 5, which sets the trigger 5 to the state of logic 1. From the output of the trigger 5, a high logical level of the signal goes to the first input of the And 7 element and to the third output of the block 1i. At time ti, the second input of the And 7 element receives a high logical level of the signal, from the output of the And 7 element, this signal is transmitted to the input of the installation at the O flip-flop 6 and the fourth output of the block 11. At the output of the flip-flop 6 a low logic level is set, which is transmitted to the second output of block 1i

7P

(it is stored on it on the rsg time, inclusive),

On the third cycle (time point to) the same switchings occur in the circuit as on the first cycle, except that the signal to the input of the installation in 1 trigger 6 is not received. On the fourth, fth, etc. by

2P

The 2nd cycle, inclusive, of block 11, functions in the same way as on the second and third, however, at the same time, the logical level of the signal arrives at the second input of the And 7 element. The operation of block 12 is different only in that its clock input receives signals that are generated at the first output of block 11.

 Unit 2 operation process | is performed as follows: at the cycles from the first to the 2nth, loading of elements is performed ° -V1-M) d (O i-guest column of the F2n transformation matrix, so that at the Km (2H) cycle, the element (K-1 , 1-1) this element is transmitted to the output at the corresponding device operation cycles (the dK element at the cycles from ())

I / “p

2), and the process ends at the 2nd cycle.

In the first cycle to the inputs from the first to

2n-th decoder 8 receives a code of 0.00.

As a result, a high logic level is generated at the first output of the decoder 8, which is transmitted to the first input of the element 10i, the second input of which receives a clock pulse. As a result, a write pulse from the output of the AND 10i element is transmitted to the write input of the register 19i, to the information input of which the element d | M is fed to the column of the transformation matrix F2n. In this cycle, the output of the block through the element OR 12 from the output of the element I 11k (at its second input - a low logical signal level) transmits a low logical signal level.

In the second cycle (time ti), the inputs 1,0, ..., 0 enter the inputs from the first to the 2nth decoder 8. As a result, a high logic level is generated at the second output of the decoder 8, which is transmitted to the first input of the AND element 102. At the same time, a clock pulse arrives at its second input, it is transmitted to the recording input of the register 92, to the information input of which the next element d 1 1 arrives column of the p2p transformation matrix. At this step, the output of the block through the AND 111 element (at its second input is the high logical level of the signal) and the OR 12 element are transferred to the register 9i- (r ° | M (the remaining inputs of the OR 12 element are logical O signals)).

Finally, on the 2 nd cycle of operation of the device, the element d (1 i-th column of the transformation matrix p2p is written in 2 nd register 9. In this case, elements from the outputs of the registers) are transmitted to the output of the block from the following sequence: on the third and fourth clock cycles the fifth is the eighth, etc., so that the K-th element of the i-th column of the F 2P transformation matrix is transmitted to the output of block 2i with (2k + 1) -th clock cycle per clock inclusive

Computing function

block 3j consider the example of the computing unit

In the first cycle (time point to), the code 0.00 arrives at the second inputs of the AND 14k elements. As a result, from the outputs of the AND 14k elements, the low logical level of the signal is transmitted to the inputs of the element OR 17. From the output of the element OR 17, the low logical level of the signal is transmitted to the second input of the adder 13 modulo two, to the first

five

five

input which receives a logical signal

 A. At this point in time to no, the shift signal in the 15k registers shifts the content one digit to the left (toward the higher bits). The signal that registers on the write / read input of the registers 15k, after 0.5 cycle, writes this content to the registers 15k (the result of modulo two is written to the first register - logical

5 O, which also goes to the second input of the element OR 16). As a result, the output of the element OR 16 produces a result (logical O), which is transmitted to the output of block 3i.

0 In the second cycle (time ti), the second inputs of the elements And 14k arrive

code 1.00. As a result, the output element

And 14t, and then the contents of register 15i are transmitted to the first input of the element OR 17,

5, the output of the element OR 17, the contents of register 15i (logical O) are transmitted to the second input of the adder 13 modulo two. At its first input comes the element of the first column of the transformation matrix.

0 F2n. At this point in time ti, the shift signal in registers 15k performs a shift of the content by one bit to the left (towards the higher bits), According to the signal sent to the record / read input of register 15k after 0.5 clock cycle from the output of delay element 18 This content is written to registers 15k. In this case, the first register is written

0 result modulo two (() 0). In addition, it also enters the second input of the element OR 16. As a result, the result of the element OR 16 forms the result d °, which is transmitted to

output of block 3i.

2 1

On the third and subsequent (2) cycles, the block 3i functions as on the second. At this element g.2n) of the first column of the transformation matrix, P% n

arrive at the second information input of block 3i in the following sequence: on the third and fourth clock cycles - element r, on the fifth - the eighth - element cr2 0, etc., so that the Kth element of the first column of the F2n transformation matrix enters () - of the second cycle according to the 2nd cycle, inclusive.

The operation of the block differs from the operation of block 3i in that its first information input signals come from the output of the 3i block, and the second information input of the 3g block receives the elements of the second column of the F 2P transformation matrix; the results generated at the output of its element OR 16 are transmitted.

Claims (1)

Claims An apparatus for solving Boolean differential equations comprising the first through the nth computing units, where n is the number of Boolean variables, the first through the nth control blocks, and the first through the nth decryption blocks, and the clock input of the device is connected to the clock input of the first control unit, the first output of the 1st control unit (where 1 1п-1) is connected to the clock input of the (1 + 1) -th control unit, the zero potential input of the device is connected to the first information input of the first computational block, output 1 th calculation the itel block is connected to the first information input (i + 1) -ro of the computing block, the first information input of the device is connected to the information input of the first decryption block, the output of the j-ro decryption block (where J-1п) is connected to the second information input of the j-ro computing block, characterized in that, in order to extend the functionality by solving Boolean differential equations, the device contains from (n + 1) -th to 2nth control unit, from (n + 1) -th to 2nth decryption unit , from (n + 1) -th to 2nth computing unit and comm utator, with the first output of the K-ro control unit (where To p2p-1) is connected to the clock input (K + 1) of the control unit, the first output of the 2P control unit is connected to the first inputs of the mode of all control units, the input of the unit potential of the device is connected to the second input of the mode of the 2th control unit, the second input of the mode of the Lb control unit ( where b 1, ..., 2n-1) is connected to the second output (b + 1) of the control unit, the second output of the first control unit is connected to the output of the device tact feature, the output of the k-th computing unit is connected to the first information input ( K + 1) -th computing unit, the output from the th decryption unit (where from p + 12P) is connected to the second information input of the cth computing unit, the output of the 2nth computing unit is connected to the control input of the switch, the outputs of which are connected respectively to the information outputs of the device, the information inputs of which are from the second to 2nth respectively to the information inputs of the second to 2nth decryption units, 1st clock The 5th input of the device group (where, ..., 2P) is connected to the clock inputs of the 1st decryption unit and the 1st computing unit, the third outputs of the control units from the first to the 2nd in-th are connected respectively to the information inputs from the first to 2n- the first group of all decryption units and to the information inputs from the first to the switch, the fourth outputs of the control units from the first to the second to the second are connected 5, respectively, to the information inputs from the first to 2nth second group of all decryption units and to information inputs from the first to the group of all computational units, each control unit containing two triggers and an AND element, and in each control unit a clock input of the control unit , the first and second inputs of the control unit mode are connected respectively to the counting input of the first trigger, to the installation input of 1 second trigger and to the first input of the And element, the output of the first trigger is connected to the first output of the control unit laziness, to the second input of the AND gate and a third output 0 of the control unit, the output of the element I is connected to the fourth output of the control unit and to the installation input in O of the second flip-flop, the output of which is connected to the second output of the control unit, while 5 each computational block contains two OR elements, 2P elements AND, a delay element, a modulo-two adder and 2P shift registers, and in each computational unit a clock input of the calculating unit is connected to the shift inputs of all shift registers and to the input of the delay element, the output of which connected to the write-read inputs of all shift registers, information 5 inputs from the first to the 2nd group of the computing unit are connected respectively to the first inputs of the elements AND from first to, the first information input of the computing unit is connected to the first input of the first OR element, the output of which connected to the output of the computing unit, the second information input of which is connected to the first input of the modulo two adder, the output of which is connected to the second input of the first OR element and to the information input of the first shift register, the output of the p-th shift register (where p 12n-1) is connected to the information input (p + 1) of the shift register and to the second input of the p-th element AND, the output of the shift register is connected to the second input of the element AND, the outputs of the elements AND are connected to the inputs of the second element OR whose output is connected to the second input of the modulo two adder, each decryption block contains a decoder, two groups of AND elements, an OR element and first to 2n registers, and in each decryption block, the information inputs of the first g the decryption unit groups are connected to the decoder inputs, the outputs of which are connected respectively to the first inputs of the elements AND from the first to the 2 nd first groups, the outputs of which are connected respectively to the write-read inputs of registers from the first to the outputs of which are connected respectively to the first inputs of the elements And from the first to the second group of the second group, whose outputs are connected to the inputs of the OR element, whose output is connected to the output of the decryption unit, whose information inputs from the first to the second group of the second group are connected From the first to the second inlet of the second group, the clock input of the decryption unit is connected to the second inputs of the AND elements of the first group, the information input of the decryption unit is connected to information inputs of all registers. at Sign mouth. IN 1 one R one FIG 4