SU1488802A1 - Device for associative loading of data vector of variable format - Google Patents

Description

The invention relates to computing and can be used in computing systems focused on associative data processing of variable format,

in vector and pipeline multiprocessor computers, as well as in automated data banks. The purpose of the invention is the extension of functionality due to the formation of

a multiple stream of data of a variable format of a vector with the set interval of values of its components. The device contains two registers, six comparison circuits, three delay elements, a NOT element, two counters, four decoders and a trigger, two switches, seven AND elements, and a clock generator. The device provides for the formation of a vector containing components of a given format, the values of which are within a specified interval, from a stream of operands of a variable format. The arrangement of the vector components is based on the analysis of the type and values of the operands with their sequential selection from the received message. The device generates a readiness signal to read the vector by the completion of the placement of its components.

or at the end of the transmission of messages “to the sources of information. 3 il.

The invention relates to computer technology and can be used in computer systems oriented towards associative processing of variable format data, into vector and multi-processor conveyor computers, as well as in automated data banks.

The purpose of the invention is to expand the functionality of the device due to the formation of a plural stream of operands of variable

vector format with a given interval of values of its components.

Figure 1 shows the block diagram of the device; Figures 2 and 3 are functional diagrams of an operand selection node and a component selection node, respectively.

The device (figure 1) contains the register 1, the switch 2, the register 3, the decoder 4, the switch 5, the group of blocks 6 elements And, the group of registers 7, circuits 8 and 9 comparison, the decoder

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comparisons, element 12,

'10, comparison circuit 13, decoder 14, element NOT 15, decoder 16, element '

And 17, the counter 18, the comparison circuit 19, the delay element 20, the comparison circuit 2.1, the And 22 element, the clock pulse generator 23, the register 24, the counter. 25, And 26, delay 27, trigger 28, And 29 element, delay element 30, OR element 31, And elements 32 and 33, output group 34 of register 1, output group 35 of the decoder 10, group of outputs 36 of the decoder 16, group of outputs 37 of the node 15 2, group of outputs 38 of the decoder 4, group of outputs 39 of the decoder 14, group of outputs 40 of node 5, group of information inputs 41 of the device, device start input 42, signal-g 20 output device 43, group of code inputs 44 devices,. group of inputs 45 of the device vector length code, input 46 of the device reset, group of information outputs 47 25

devices, the device ready output 48, and the group of outputs 49 of the device vector length,

Switch 2 (Fig. 2) · contains groups of blocks of 50 elements And and a group of 30 blocks of 51 elements of OR.

Switch 5 (fig.Z) contains groups of 52-element AI blocks a group of OR blocks 53.

Principles of construction and operation of the device.

The initial state of the device is characterized by the fact that the trigger 28, the counters 25 and 18 are set to the state "0" (not shown). 40

If necessary, use the device at the inputs 44 in the register 3 is the word containing four fields. The first field indicates the type of the operand, in the second field the format of the vector components, in the third and fourth field the initial and final values of the boundaries of the interval of vector components, respectively.

According to 'Inputs 45 in register 24 the binary code of the required vector length is entered.

Accompanied by a start pulse, which enters input 42, is fed to inputs 41 sequentially, $$ current messages. Each message contains several fields. In the first field, the type of operands is indicated, in the second, the format, and in the third, if

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number of operands of the specified format. The data field contains operands of the same format. In this case, the maximum size of the data field of register 1 is selected in accordance with the minimum format of the operand message.

The device must provide a search in the message flow of operands of a specified format, and the value of the operands must belong to the specified interval. From the selected operands, a vector is then formed containing the components of the specified format. In this case, the maximum format of one component of the vector must correspond to the maximum format of the input operand.

In this example, the number of output registers 7 is selected for two components of the maximum format. Thus, the output registers 7 can accommodate a vector containing two components of the maximum format, four components of the average format, eight components of the minimum format.

Under these conditions, the device operates as follows.

Let it be necessary to form a vector - containing eight components of the minimum format, and the input of 41 devices receives a stream of messages with operands of various formats. At the same time in the register 24 is set the code number eight.

The interaction of the device with the source of the operands is made by the system "Request-response", eliminating the loss of information.

As a request signal, a single signal from the zero output of the trigger 28 is used, which arrives at the output 43 of the device. On this signal, the source of information issues a message on input 41 accompanied by a trigger on input 42. By a trigger signal acting as an answer signal, trigger 28 is set to state "1". And a single signal from a single output of trigger 28 opens element 26 and through Allowed the flow of the generator pulses 23 to the circuit elements of the device.

Let in the register 3 the codes of the type of operands П are set, and the limits of the interval А „and А _к , and in the register 1 there are 5 1488802 6

Operands of type P, minimum format are given.

In this case, since the operand of the required type P ,, is received in register 1, the comparison circuit 13 generates a single signal at the output "Equal". At the same time, the formats of the operands of the message and the required register 3 are compared in the comparison circuit 11, also in this 10 case forming a single signal at the "Equal" output. A single signal from the output of the element And 12 opens on the second direct input element And 17, is blocked. on the inverse 15 input element And 32 and allowed to decrypt the format code with the decoder 10.

Since in register 1 there are operands with the minimum format, then 20 at the output 35 _{0 of the} decoder 10 a single signal is formed, which blocks 50 ,, elements AND switch 2 are opened.

Switch 2 operand provides signals from the output of the decoder) 0 sequential transmission of operands from the data field of register 1 through blocks 51 elements OR outputs 37 to write them to registers 7 in the case of belonging to a specified interval of values.

The choice of the minimum format operand is made by the signals of the decoder 16.

Since the counter 18 is in the zero state at the output of the decoder 16, 36 _On a single signal is generated, which is open unit 50 _{3 |} elements And in the switch 2. At the same time, the operand from the data field of the outputs 34, through the block 50 elements AND, connected by assembly OR to the remaining blocks of the elements AND of this group, is transmitted through block 51, the elements OR to the output 37,. Such a connection of the outputs Allows you to move the operand from anywhere in the data field of register 1 to the beginning, i.e. shape it on outputs 37 ,.

> Operand from outputs 37, goes to the first inputs of circuits 8 and 9 comparison.

Let the register 3 set the boundaries of the interval A _n and A _k , and the first operand A _o lies in the specified limits, <lah. I

At the same time, ₄ since А „= А _n , at the output" Less "of the comparison circuit 8 of the forms · ·" Part. · The zero signal is generated, and in view of the fact that A ₀ ? A _k , then at the output "More""Comparison circuit 9 is also present zero signal. Therefore, the element And 17 is open on both inverse inputs.

The counter 25 is in the zero state while at the output of the decoder 14, 39 _On a single signal is generated, which is open unit 52 and the switch elements 5.

This node provides the transfer of the selected component by the signals of the decoder 14 and through the open blocks of 52 elements AND signals from the outputs 38 of the decoder 4 in accordance with the set format in register 3.

In the above case, the output g 38 _O 4 decoder unit signal is formed, which blocks visible · 52 ^. Therefore, the operand is transmitted through the block 53, the elements OR to the outputs 40, the switch 5 and further to the inputs of the block 5, the elements I.

The pulse generator 23, passing through the element And 26, the element 27 of the delay and the element And 17, the first component is written to the register 7,.

30 delay Element 27 is necessary to coordinate the time of receipt of the pulse. Generator at the inputs of the elements And 6 with the time of the transient processes in the transmission of the operand from register 1

35 and determining its belonging to the required range of values.

. The delayed element of the delay element 20 in the counter 25 is added one at a time, since

40 at the output "More" of the comparison circuit 19, there is a single ¹ signal, and through the And 22 element, the counter 18 also adds a unit for the pulse passing the delay element 30.

45 At the "More" output of the comparison circuit 21, a single signal is held, which opened the elements of the th 17, 32 and 33. At the "More" output of the comparison circuit 19, there is also a single signal,

50 closing element And 29 on the inverse entrance. Why trigger 28? does not change its state.

The output 36, the decoder 16 generates a single signal, which 55 operand from the data field of register 1 is transmitted through the open block 50 _{32 of the} switch 2 through the block 51 _{g of the} elements OR to the outputs of 37 _g and further considered order, but already open

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elements And 5 2 _{g1 a} single signal from output 39, decoder 14 through block 53 _g to outputs 40 _{2 of} switch 5, and then to the inputs of elements I. Then the changes in the states of the circuit elements are made according to the generator pulse as described above.

The transfer of the operand from register 1 to the next register 7 is not performed in cases when the value of the next operand of this format does not belong to the specified interval 'values in register 3 and when the type of the received operand in register 1 is not the required one in register 3.

In the first case, when the value of the next operand is less than A _m , the comparison circuit 8 generates a single signal at the “Less” output. If the value of the operand is greater than A _c , then the comparison circuit 9 at the output of "More" forms a single signal. In both cases, the element And 17 is closed, and the number from the register .1 in the next register 7 is not transmitted. At the same time, the contents of the counter 25 does not change, but in the counter 18, the next unit is added and a new clock cycle of the next operand is organized.

If the value of counter 18 is set equal to the value of the register field 1, then the comparison circuit 19 at the output of “More” generates a zero signal, the opening element AND 29. At the same time, delayed pulse by delay element 20 simultaneously with the addition of one in counter 25 is set to the state “0” counter 18 and, if the output "Bolytse" comparison circuit 21 there is a single signal ¹ indicating the formation of non-discharge of the vector, the trigger 28 is set to "oN" via the outdoor · aND gate 33 and OR gate 31. As with the unit chased from the zero output of the trigger 28, made a request the next message.

In the second case, when the type of the received operand is different from that set in register 3, a zero signal is generated at the "Equal" output of the comparison circuit 13, which closes through element 12 and element 17. At the same time, the contents of counter 25 does not change and the delayed signal element 30 delays through an open element AND 32Г * at the inverse input with a zero signal with "· ¹ output element And I 2 and element OR

31, the trigger 28 is set to the state "0", requesting the next message.

The device generates a ready signal at the output 48 in cases when the code of the number of the required number of vector components is preset in the register 24 and the source of the messages has completed the transmission of information.

In the first case, after the transfer of the next operand to the register 7, in the counter 25 a code of the number of the required number of vector components is generated. In this case, a single signal from the output "More" 'of the comparison circuit 21 is removed, closing the elements And 17,

32 and 33, with the result that trigger 28 remains in state "1", and a single signal appears at output 48.

Since there is no single signal at the output 43, a request for the next message is not produced, and a single signal from the output 48 loads the vector, the length of which can be read from the outputs 49.

In the second case, the source of information on input 46 generates a signal that sets register 24 to “0”. In this case, the single signal from the output of the “More” comparison circuit 21 is removed, forming a single signal at output 48, determining the above reading order of information from devices.

If required to generate the vector format with secondary components, for analysis of the operands are transferred over open _α blocks 50 and the switch elements 2. In this case the unit of signal output from the decoder 16, 36 _On analysis on operands received through blocks 50 i50 _r1, and the signal output from 36, through open blocks 50 and 5024, since with this format only two operands can be placed in register 1.

The transfer of these operands, if they belong to a given interval of values, is performed through blocks of 52 ₂ πό signals from the outputs 39 ₀ , 39 ,, 39 _g , 39 _? , since registers 7 can accommodate four components of this format.

Similarly, when forming a vector with components maximal9 ία;

Only one operand of register I is transmitted via the decoder signal from output 36 _O through open blocks 50 ₍ switch 2. The analysis of the operand's belonging to the set interval is performed similarly to that considered, and the component is recorded through open blocks 52 ₄ elements AND by the output 38o and by two signals of the decoder 1 4 - from outputs 39 _O and 39,.

If necessary, the formation of vectors with components of different formats, the device is brought to its original state.

If you want to form a vector, the value of the components of which is within the entire range of values, then in the third field of the values of register 3 a zero code is set, and in the fourth field - the maximum code (units in each field bit). In this case, for any value of A in the register. 1 at the outputs "Less" of the comparison circuit 8 and "More" of the comparison circuit 9, zero signals are formed that hold the AND 17 element in the open state.

Claims (1)

Claim A device for associative loading of a variable format data vector containing a first register, a group of information inputs of which is a group of inputs of a device’s message flow, a second register of data, a group of information inputs of which is a group of inputs of operand type codes and device interval boundaries The outputs of which are connected to the information inputs of the same name registers of the group, the outputs of which are groups of outputs of the device data vector, four schemes comparison, two delay elements, two elements AND, the element NOT, the third register ·, information inputs and the reset input of which are, respectively, a group of inputs of the device vector length code code and a device reset input, the first counter, whose output group is a group of device vector length code outputs the first decoder and trigger, the unit input of which is the input for 12 10 start the device whose output has a request connected to the zero output of the trigger, the first group of outputs of the second register is connected to the first group of inputs of the first comparison circuit, the second group of inputs of which is connected to the first group of outputs of the first register, the input element is NOT connected to the output of the second comparison circuit, the first the group of inputs of which is connected to the outputs of the third register, the second group of inputs of the second comparison circuit is connected to the inputs of the first decoder and to the outputs of the first counter, the counting input of which is through the new delay element is connected to the control inputs of the blocks of elements AND of a group and with the output of the first element I, the first and second inverse inputs of which are connected to the outputs of the third and fourth comparison circuits, respectively, the second and third groups of outputs of the second register are connected to the first groups of inputs of the third and fourth respectively comparison circuits, the output of the element is NOT the output of device readiness, characterized in that, in order to extend the functionality. due to the formation of the opera Dov variable format vector with a given interval of values of its components, it introduced the second, third and fourth decoders, the fifth and sixth comparison schemes, the third, fourth, fifth, 'sixth and seventh elements And the first and second switches, "the second counter, the third the delay element, the OR element and the clock pulse generator, the output of which is connected to the first input of the second element AND, the second input of which is connected to the single output of the trigger, the zero input of which is connected to the output of the OR element, the first and second inputs of which Connected to the outputs of the third and fourth elements And, the first inputs of which are connected to the first direct input of the first element And to the output of the second 'comparison circuit, the inverse input' · 'of the third element And connected to the second direct input of the first element And, with the synchronization input of the second the decoder and the output of the fifth element And, the first and second inputs of which are connected to the outputs, respectively, of the first eleven .1488802 I 2 and the fifth comparison circuit, the first group of inputs of the fifth comparison circuit is connected to the inputs of the second decoder and the second group of outputs of the first register; the second group of inputs of the fifth comparison circuit is connected to the inputs of the third decoder and the fourth group of outputs of the second register; the third group of outputs of the first register is connected to the first group of inputs of the sixth comparison circuit, the second group of inputs of which is connected to the inputs of the fourth decoder and the outputs of the second counter, the reset input (5 of which is connected to the second input of The second element And to the output of the sixth element "And, the inverse input of which is connected to the output of the sixth comparison circuit and to the first input 20 of the seventh element And, the second input of which is connected to the input of the second delay element and through the third delay element - to the output of the second element And, the output of the second delay element - 25 is connected to the third input of the third element I, the third direct input of the first element I is connected to the output of the third delay element, the output of the seventh element I is connected to the counting input of the second 'counter, the direct input of the sixth The terminal I is connected to the output of the first delay element, the groups of information inputs of the first switch are connected to the output groups of the first register, starting with the fourth, the first „and second groups of equal inputs of the first switch are connected respectively to the output groups of the second and fourth decoders, the output group of the first switch is connected with the second groups of inputs of the third and fourth comparison circuits and with the group of information inputs of the second switch, the first and second groups of control inputs of which are connected S with the outputs of the first and third decoders, respectively, each group of outputs of the second switch is connected to a group of information inputs of the block of the same name and the elements of the group. 1 1A88802 Fig 2 1488802