SU1339562A1 - Data associative loading device - Google Patents

Abstract

The invention relates to computer technology and can be used in computer systems oriented towards associative information processing, as well as in automated data banks. The purpose of the invention is to expand the scope of application by forming arrays of the same type data from a multiple input stream of operands in a given interval of values. The device contains an input operand register, a group of blocks of elements AND, a block of elements AND, a group of output registers, a comparison circuit chip, a delay element, two elements AND, a counter, a decoder and a control trigger. The device forms a fixed format output data array of one type in two modes. In the first of these, this array contains data, the values of which are within the established values, and in the second, the array contains data, the values of which are limited by a range of values, 1 sludge. § (L with with SP

Description

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The invention relates to computing and can be used in computer-oriented systems. associative information processing, as well as in automated data banks.

The purpose of the invention is to expand the field of application by forming arrays of the same type data from a multiple input stream of operands in a given interval of value.

The drawing shows a block diagram of the device.

The device contains an input register 1, a register of operand type 2, a comparison circuit 3, a block of 4 And elements, a group of blocks of 5 And elements, a group of output registers 6, a circuit of 7 compared

The comparison circuit 8, the trigger 9, the one-shot 10, the element 11, the delay element 12, the second element 13 delay, the element 14, the circuit. 15 comparisons, decoder 16, NOT element 17, array size register 18, counter 19, device information input group 20, device start input 21, device signal output 22, device reset input 23, device code input group 24, size code input group 25 device array, group of information outputs 26 of the device, output 27 of device readiness, group of outputs 28 of the size of the device array.

The principles of construction and operation of the device are as follows.

The initial state of the device is characterized by the fact that the trigger 9 and the counter 19 are set to the state O (not shown).

If the device needs to be used, the inputs 24 in register 2 are supplied with a word containing three fields. The first field indicates the type of the operand, and the second and third indicate the initial and final values of the limits of the interval of operand values, respectively. The inputs 25 to register 18 enter the required size of the output array. The inputs 20, accompanied by a trigger signal arriving at input 21, are successively supplied with an array of input data — operands, Each operand contains two fields. In the first field, the type of ss of the held second field is indicated.

The interaction of the device with the source of the operands was performed using the Request-Answer system, which eliminates the loss of information.

A single signal from the zero output of trigger 9 is used as a request signal. According to this signal, the information source carries an operand, followed by a trigger signal acting as a response signal. With this signal, trigger 9 is set to 1. A one-shot 10, which generates a single pulse, is triggered from a single output of trigger 9.

Let the register 2 set the type codes of the operand P., and the bound

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terval A and A, and in register 1 there is an operand of the type P., whose value is AC (A ;,) AI.

In this case, since the operand of the required type P, is received in register 1, the comparison circuit 3 generates a single signal at the output Equal to which the number A is transmitted through the AND 4 elements to the first inputs of the comparison circuits 7 and 8, as well as to the inputs of all blocks of 5 elements I.

Since, then, at the output of MeHtd, above the comparison circuit 7, a zero signal is generated, and in view of the fact that m, then at the output. More comparison circuit 8 is also present zero signal. Therefore, the element And 11 is open on both inverse inputs. The counter 19 is in the zero state, and at the same time, at the zero output of the decoder 16, a single signal is generated, which opened the And 5 elements of the first block.

Since in register 18 the binary code of the size i of the array is set (within 1, ..., p), then in the V-code More comparison circuit 15 a single signal is formed that opens the AND 1-4 element at the second input.

By a one-shot pulse 10 passing through the open element 11 and the code of the number A, is taken to the register 6 4 through the elements 5. After some time, determined by the delay element 13, in the counter 19, add-. unit is.

If the code is in the counter 19. less than the register code 18, then the output of the More comparison circuit 15 maintains a single signal level by which the And 14 element is held in the open

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state, and the output of the element is NOT 17 remains a zero signal. The delayed pulse element 12 of the delay is set to O trigger 9.

A single signal from the zero output of the trigger 9, which is fed to the input 22, is used to query the next operand. Further, the operation of the device is carried out similarly, if the value of the number A is in the range of acceptable values.

The transfer of the operand from register 1 to the next register 6 is not performed in the following cases: the type of the received operand in register 1 is different from the value specified in register 2j of the received operand in register 1 does not belong to the specified value interval in register 2.

In the first case, a zero signal is generated at the output of Equal to the comparison circuit 3, therefore, at the first inputs of the comparison circuits 7 and 8

zero code. At the same time, the output of the Menu-25 forms a single signal at the output 27 of the unit 7 of the comparison circuit 7, a single signal is generated, and at the output of the More circuit of the comparison 8 - a zero signal. A single signal from the output. Less than the comparison circuit 7, the element 11 is closed at the first inverse input. Therefore, the operand from register 1 to the next register 6 is not transmitted, the contents of counter 19 does not change, and the output of the More circuit 15 compares a single signal. In this case, by the delayed pulse, the delay element 12 is set to O flip-flop 9. By the single-7 signal from output 22, the next -perande is requested.

In the second case, when the value of the number received in-register 1 is less than A ", the comparison circuit 7 generates a Smaller signal at the output. If the value of the number is greater than Aq, then circuit B of the Comparison at output More generates a single signal. In both cases, the And 11 element is closed, and the number from register 1 is not transferred to the next register 6, and the trigger 9 is set to O, requesting the next operand.

The device generates a ready signal at the output 27 of the output load.

This code defines the further considered reading of information from the device.

If it is necessary to form 30 the next array, the device is brought to its initial state.

If it is required to form an array of data of the same type within the entire range of permissible values, then in the second field of register 2 a zero code is set, and in the third field - the maximum (units in each bit field). At the same time, for any value of A in register 1, at outputs less than comparison circuit 7 and more comparison circuit 8, zero signals are formed that hold element 11 in the open state.

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Claims (1)

Invention Formula A device for associative data loading containing an input register whose input group is a group of information inputs of a device, an operand type register, whose input group is a group of device code inputs, AND blocks, AND block, output registers whose outputs are groups of information of the array of codes 26 in the following cases of the device outputs, four schemes of time x: counter 19 is set for the code, the first delay element, two And, the counter whose output group is an output group numbers K; the source of information has completed the transmission of the operands, in the array 0 which required type was less than K. In the first case, after sending the Kth number to register 6, the code 19 generates the code K. In this case, from the output of the More comparison circuit 15, the single signal is removed, closing the AND 14 element, as a result of which the trigger trig ger 9 remains in the single state A single signal appears at output 27. Since there is no single signal at the output 22, the request of the next 5 operand is not made, and a single signal from output 27 loads the output array, the format (size) of which can be calculated from output 28. In the second case, the source of information on the input 23 introduces a signal that sets the register 18 to 0. In this case, a single signal from the output of the More comparison circuit 15 is removed. 0 This code defines the further considered reading of information from the device. If it is necessary to form 0 the next array, the device is brought to its initial state. If it is required to form an array of data of the same type within the entire range of permissible values, then in the second field of register 2 a zero code is set, and in the third field - the maximum (units in each bit field). At the same time, for any value of A in register 1, at outputs less than comparison circuit 7 and more comparison circuit 8, zero signals are formed that hold element 11 in the open state. five 0 45 50 Invention Formula A device for associative data loading containing an input register whose input group is a group of information inputs of a device, an operand type register, whose input group is a group of device code inputs, AND blocks, AND block, output registers whose outputs are groups of information  device outputs, four times schemes, the first delay element, two the device array size code, the decoder and the trigger, whose single input is the device start input, the signal output of which is connected to the zero output of the trigger; its zero input is connected to the output of the AND element, the first output group of the operand type register is connected to the first input group of the first comparison circuit, the second group of input of which is connected to the first group of input register, the second group of outputs of which is connected to the group of inputs of the block of elements AND, whose control input is connected to the output Equals the first comparison circuit, the output group of the block of elements And is connected to the groups of inputs of the blocks of elements AND of the group, the outputs of which are connected to the inputs of the same output registers of the group, the outputs are connected to the inputs of the decoder, the i-th output of which (, 1, ..., p-1 ; n the number of output registers of the group) is connected to the first control input of the (1 + 1) -th block of elements AND of the group, characterized in that in order to expand the field of application by forming arrays of the same type data from a multiple input stream of operands of the same type meaning element, the element NOT, the second delay element, the one-shot and the array size register, the information inputs five five 0 0 6 which are the inputs of the device array size, the reset input of the array size register is the device reset input, the single-oscillator input is connected to the single control trigger output, the single-oscillator output is connected to the forward input of the second element, and through the first delay element to the first the input of the first element is And, the second input of which is connected to the input of the element NOT and with the output Bolle of the second comparison circuit, the first group of inputs of which is connected to the outputs of the array size register, the second group of inputs of the second circuit The equal is connected to the outputs of the counter, the counting input of which through the second, the delay element is connected to the second control inputs of the blocks of elements AND of the group and with the output of the second element I, the first inverse input of which is connected to the output Less than the third comparison circuit, output More than the fourth comparison circuit, the first groups of inputs of the third and fourth comparison circuits are connected to the output group of the block of elements And, the second and third groups of outputs of the register of the operand type are connected to the second groups respectively, and inputs of the third and fourth comparing circuit respectively, an output of NOT is the output device is ready. 26i Editor E. Papp Compiled by M. Kudr Shev Tehred M. Dvdyk . Order 4223/39 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader M.Sharoshi