SU1425704A1 - Device for compressing vectors - Google Patents

Abstract

This invention relates to automation and computing. The purpose of the invention is to expand the functional possibilities by eliminating restrictions on the size of the components of the information vector. To achieve this goal, a device for compressing vectors contains a matrix of cells of m rows and n columns, each cell containing a logical block 18 containing two elements AND 19, 20, element OR 21, two elements HE 22, 23, trigger 24, cells 4 are connected in a matrix by control connections 9-14, two blocks 15, 16 of elements AND, register 17 and; information links 5-8. 2 ill., 2 tab. (L

Description

Inventive, e refers to special devices for processing information in digital computers, devices of matrix or vector calculations, devices for translating from one language to another.

The purpose of the invention is the extension of functionality due to the removal of restrictions on the size of the information vector components.

FIG. 1 shows a block diagram of a device for compressing vectors in FIG. 2, a functional diagram of a cell.

A device for compressing vectors contains a group of information inputs 1, a group of inputs 2 features, a group of outputs 3, ha xp cells 4 (t is the number of rows, n is the number of columns), and each cell 4 contains the first 5 and the second 6 information inputs , the first 7 and second 8 information outputs, the first 9, the second 10 and the third and control inputs

the first 12, the second 13 and the third 14 control outputs, the first 15 and the second 16 blocks of elements And reg and 17, logic block 18, containing the first 19 and second 20 elements AND, element 21 OR, the first 22 and second 23 elements NOT, trigger 24

Device for compressing vectors

I

works as follows.

A single value is fed to the i-th input (i 1 - n) of the matrix control input 2 of the matrix if the output of the device requires memorizing the value of the i-ro information input from the group of inputs 1. If the input value arriving at the i-th information input , it is necessary to mask (exclude), then on the 1st input of the group of control inputs 2 of the matrix a zero value is applied. At the same time, the logical data zero is fed to the second information 6 and the control unit 10 of the first columns of the matrix, and the third control input; The 11 cells of the last (nth) column are fed to a logical one. The original information vector enters through the group of information inputs 1 and the first information inputs of 5 cells of the first row of the matrix to the information inputs of the first group of 15 I elements, and their control inputs through the group of inputs 2 and the first control inputs of 9 cells receive a control binary vector. The value of i-ro rating, Dov

g

50

five

0

five

0

five

0

five

The number of control of its vector from the input 9 cells simultaneously with the value of the left (i-1) and right (i + 1) bit from the inputs 10 and 11 of the cell, respectively, also goes to the input of the logic unit 18.

In each clock cycle, the clock inputs of all the triggers 24 and the registers 17 of the cells 4 are given a clock pulse. As a result, the information and control vectors are stored in a transformed form in the cells 4 of this line and, from their output, are fed to the inputs of the next line. The transformation of the control vector is reflected in Table. 1 and 2.

The transformation of the information vector is performed as follows. In register 17, by pulse 1, information can be written both from the first 5 and from the second 6 information inputs. Transfer to the information entry status register 17

5 cells through the first block of 15 elements AND is possible only if the value of the corresponding () bit of the control vector at input 9 is equal to one. In this case, a single value at input 9 blocks the transfer to the input of register 17 information from the input

6 (Table 1). The transfer of information to the register 17 of the state of the second information input 6 cells is possible only if the value of the (i-1) -th bit of the control vector (input 10) is equal to one, and i-ro (input 9) is zero (tab. 1), i.e. In each row, the cell of the current column is assigned and written to the register 17 of the components of the information vector, which corresponds to a nonzero value of the control vector bits, and also the transfer and writing to the register of the cell of the right adjacent column in register 17 vectors () to the right of which are equal to zero

From tab. 2 it can be seen that at the output of trigger 24 of the i-ro column of the matrix of the current row, the zero value of the 1st bit of the control vector goes to one, if the value of the (i- -1) -th bit of the control vector is equal to one, the single value goes to zero if the value of the (i + 1) -th bit of the steering vector is zero; in the remaining cases |

the value of the control vector is written unchanged.

Thus, in each cycle, the information and control vectors are rewritten in the next line, transformed in such a way that the nonzero components of these vectors are shifted to the right by one position to the place of the zero components. It is obvious that for n steps (in the worst case), the n-dimensional information vector is compressed. The result of the compression is in the registers 17 of the row and at the outputs of the 3 matrix.

The sequential compression of a plurality of information vectors is performed by the device in a pipeline mode as follows.

Since in the second cycle the partially transformed information and control vectors are transmitted to the second row, informational and control vectors can be fed to the informational 1 and control 2 inputs of the device. In the third cycle, the first informational and control vectors are transmitted to the third line. , the second information and control vectors are transmitted to the second row, and the third information and control vectors can be fed to the information 1 and control 2 inputs. Starting from the n-th path, from the outputs of 3 matrices in series with an interval of € results of compression of the first, second, and other information vectors are output.

Claims (1)

Invention Formula A device for compressing vectors containing a matrix of cells of m rows and n columns, each cell containing two elements I, an NL element, two NOT elements and a trigger whose output is the first controlling output of the cell, the first controlling input of which is connected to the second and the third control outputs are the terminals P, the first input of the first element I, the input of the first element NO, the output of which is connected to the first input of the second element I, the output of which is connected to the first input of the component STI, the output of which is connected to the input of the trigger setup ra and entrance Q 5 0 5- Q five 0 five 0 five 704 the second element of the PC, the output of which is connected to the cfipoca input of the trigger, the synchronization input of which is connected to the synchronization input of cGs, the second control input of which is connected to the second input of the second element And, the third control input of the cell is connected to the second input of the first element And, the output which is connected to the second input of the OR element, the first control output of the (i, g) -th cell (i 2, m - 1, j 2, p - O is connected to the first control input of the (i + 1, j) -th cell , the second control output of the (i,) th cell is connected to the third control input of the (i, j - 1) -th cell, the third control Its output is connected to the second control input of the (i,) -th cell, the third control terminal of which is connected to the second control input of the (i, j + 1) -th cell, the second control output of which is connected to the third control input (1,) cell, the first control output (i - 1, j) fi cell is connected to the first control input (i, g) cell, the first control input (1, k) -H cell (k 1 , p) is connected to the kM control input of the device, characterized in that, in order to extend the functionality by eliminating restrictions on the size of the com Onent of the information vector, two blocks of I elements and a register are entered into each cell of the matrix, the information output of which is connected to the first information output of the cell, the first information input of which is connected to the first input of the first block of elements AND whose output is connected to the information input of the register, the output of the second block And elements and the second information output of the cell, the second information input of which is connected to the first input of the second block of elements And, the second input of which is connected to the output of the second element nta And, the first control input of the cell is connected to the second input of the first block of elements And, the register entry input is connected to the cell synchronous input, the first and second information inputs of the (L,) -th cell are connected to the first and second information outputs (i-1, j ) -yi (i, j - 1) -th cells, respectively, the first and second information outputs (i,) -th someone514737046 ki are connected to the first and second information input devices of the device, the first by the input inputs (i 1, j) -A and the information output of each (m, k) -ft (i, j + 1) cells, respectively, the first information input of each (1, and) cell is connected to the k-th information cell and is connected to the k-th information (device output. cells connected to the k-th information (device output. Cell Inputs ten About About 1 1 n 1 about 1 Control logs oh oh 1 о о 1 1 Table 1 Input A logical block 18 about about 1 about table 2 Output B logic block 18 about about about 1 1 1 about 1 Phie.1