SU1619330A1 - Device for monitoring operatorъs performance - Google Patents

Abstract

The invention relates to automation, in particular to devices for training operators $ and can be used by the I / V when preparing employees of the passport office to work on an automated workplace, built on the basis of a personal computer. The purpose of the invention is to improve the accuracy of the device. The goal is achieved by selecting errors during operational data entry and their prompt elimination, which is ensured by introducing the second decoder 9, the third 18, the fourth 19 and the first 20 delay elements, the error selector 2 and the second register} 5 into the device containing the first register 4 , memory block 1, elements AND 3-13, trigger 14, element OR 15, counter 6, elements OR 7, delay elements 16 and 17 with circuit interconnections, 4 or less, on s (L 51 o with OZ Figure 1

Description

The invention relates to automation, in particular, to devices for training operators, and can be used in preparing employees of the passport office to work in an automated workplace built on the basis of a personal computer.

The purpose of the invention is to improve the accuracy of the device.

Figure 1 shows the functional diagram of the device; Fig. 2 illustrates an example of a specific embodiment of a memory block; FIG. 3 is an example of a specific constructive implementation of an error selector; 4 shows timing diagrams for the operation of the device.

The device (Fig. 1) contains a memory block 1, an error selector 2, a group of elements And 3, a first 4 and a second 5 registers, a counter 6, a group of elements

OR 7, the first 8 and second 9 decoders, the first 10, the second 11, the third 12 and the fourth 13 elements AND, the trigger 14, the element OR 15, the first 16, the second 17, the third 18, the fourth 19 and the fifth 20 delay elements.

Memory block 1 (FIG. 2) contains registers 21-23, elements AND 24-26.

The error selector 2 (FIG. 3) contains decoders 27-29, memory blocks 30-32, elements AND 33-41, triggers 42-44. In addition, Fig. 1 shows information inputs 45 and 46, synchronizing inputs 47 and 48, information outputs of the first group 49, the second group 50, and control output 51.

FIG. 2 shows information input 52, address inputs 53-55, synchronization 56 and installation 57 inputs and information output 58.

On fig.Z shows the sync 59 and installation 60 inputs.

The device works as follows.

I

The functional implications of pa-

A passport office attendant has the ability to solve the functional tasks of issuing a passport, residence permit, discharge, etc. using the automated workplace of the passport office employee.

For this, the employee of the passport office (operator) should be able to prepare a codogram - a message according to the corresponding functional task, so that these data can later be used to update the database.

The entire sequence of codes that the passport operator must form is formed in a predetermined sequence, for example, the code of the codogram number is first generated, then the code of the sending object, then the object identifiers, and the like.

For this purpose, the operator first dials on the keyboard the code number of the codogram that arrives at information input 45 of register 4, and then presses the Enter key (not shown), the signal from which arrives at the synchronization input 47 and writes the code to register 4, from the output of which is fed to the input 52 of the memory unit 1 (FIG. 2).

After a delay on the element 16 at the time of writing the code in the register 4, the same clock pulse arrives at the clock input 56 of unit 1, the address inputs of which are connected to the corresponding outputs of the decoder 8.

Considering that counter 6 and register 5 are now reset to zero, then the input of the decoder 8 will be a zero code and a high potential at its extreme output will open at input 53 a group of elements AND 24 of block 1.

The synchronizing pulse from input 56 of block 1, arriving at the synchronous input of elements And 24 and register 21, rewrites the contents of register 4 into register 21. Thus, in the register 21, the codogram number will be generated

In addition, from the output of the element 16, the sync pulse arrives at the input of the element 17, where it is delayed by the recording of the codogram number in the register 21, and then enters the input of the And 10 elements opened by another input with a high potential from the inverse output of the trigger 14.

Passing through the element And 10 to the input of the counter 6, this clock increases the address by one. As a result, register 22 is connected to the information outputs of register 4 via elements AND 25.

Then the operator on the control panel dials the code of the object number, which through input 45 enters register 4, and then presses the Enter button, from whose contacts the sync5 16

the pulse from input 47 is fed to the synchronous input 47 of register 4 and writes the next code into it.

In the manner described above, this code is then recorded in register 22 and the process of recording all the components of the codeogram continues until the output of the transfer of counter 6 does not receive a pulse, indicating that all components of the codegram are ready and are in registers 21-23.

If the code decoded by the corresponding decoder 27-29 by the operator is correctly typed (ie, such code is among the set of codes that the operator dials), then the corresponding output of the decoder 27 will be opened, for example, element 33.

Then the transfer pulse from the output of the counter 6 passes to the input 59 of the selector 2 and further, through the element 33, to the input of the reading of the fixed cell of the block 30, made in the form of a constant memory. In the fixed cells of block 30, 1 is recorded, if the dialed code exists in the set of codes or O, if the dialed code in the set of codes is not.

From the output of the fixed cells of all the blocks 30-32, in which 1 is stored, the read signals are sent to the single inputs of the flip-flops 42-44, the output potentials of which are fed to. outputs 50 in the form of correct and incorrectly dialed codes.

In addition, the outputs of the triggers 42-44

connected to the inputs of the decoder 9, which in the presence of high potentials at the output of all flip-flops 42-44 gives a high potential to the input element AND 12. The presence of any other codes at the input of the decoder 9 any other codes will lead to a high potential at the output of the element OR 15 will be fed to input element and 11.

Assuming that all components of the codogram were correctly typed, then the high potential from the output of the decoder 9 will open element I, to another input which receives a pulse of transfer of counter 6, which is delayed by element 18 for the response time of the decoder 9 and triggers 42-44.

Passing the element 12, the pulse arrives at the zero input of the trigger 14, confirming its zero state,

0

five

0

five

3306

and then, after the delay by element 19 for the trigger trigger time 14, is supplied to the pulse input of the element And 13, which is opened by a high potential from the inverse output of the trigger.

Passing the cherbz element 13 13, the sync pulse, firstly, arrives at the pulse input of the elements 3 3, rewriting the contents of all the registers 21-23 at the output 49 of the device. Secondly, it enters through the input 60 of the selector 2 and resets all the triggers 42-44. Thirdly, the same impulse after a delay on element 20 for the time of code census on output 49 goes to zero inputs of registers 4 and 5, counter 6 and through input 57 to reset registers 21-23.

If at least one of the components of the codogram is typed by the operator incorrectly, then the high potential from the output of the OR 15 element will be open to the AND 11 element.

In this case, the transfer pulse from the output of the element 18, having passed the element AND 1 1, goes to the single input of the trigger 14 and sets it in the single state.

Potential potential with a single output of trigger 14 is supplied.:; the output .1 of the device, the signal that the codogram is typed incorrectly, and the output potentials at the outputs 50 specifically indicate which component of the codogram is typed incorrectly.

To correct an error, the operator on the control panel must press a key with the name of the component of the code pattern that was typed in error. Pressing the key presses that the code of the position of the components in the codogram arrives at the input 46, and the sync pulse arrives at the input 48,

which this code writes to register 5.

The code from the output of register 5 through the elements OR 7 is fed to the inputs of the decoder 8, which to the outputs of register 4 connects the corresponding register 21-23, to which a correction must be made.

After making corrections to the corresponding component of the codogram, the e-operator sends the typed codogram to the address of the superior ACS object as described above.

Thus, the invention allows to significantly increase the effective 0

five

0

five

0

Claims (1)

the training of operators through pea-iiza- tion of the possibility of selecting and correcting errors in codograms — messages. Invention Formula A device for controlling operator operation, comprising a first decoder, the outputs of a group of which are connected to the corresponding inputs of the OR element, the first delay element, the output of which is connected to the synchronous input of the memory unit and the input of the second delay element, a trigger whose inverse output is connected to the first inputs of the first and second And elements, counter, first register, group of elements OR, group of elements AND, third and fourth elements AND, differing from the fact that, in order to improve the accuracy of the device, the second decoder is entered into it A tor, whose inputs are connected to the inputs of the corresponding elements OR groups and the outputs are connected to the corresponding address inputs of the memory unit, the information inputs of which are connected to the corresponding outputs of the first register, whose information inputs are with the corresponding inputs of the first group of the device, and the synchronous input - the first synchronous input device and is connected to the input of the first delay element, the third delay element, the input of which is connected to the overflow output of the counter, and the output to the first inputs of the third el ment and a fourth AND gate AND, the second input of which is connected to the first VYH.ODU deshif- Rathore, and an output - to a zero entry the trigger, the single output of the trigger is the control output of the device, and the single input is connected to the output of the OR element, the fourth delay element whose input is connected to the output of the fourth And element ,. and the output to the second input of the second element I, the output of which is connected to one input of the elements AND group, the other inputs of which are connected to the corresponding outputs of the memory unit, and the outputs are the corresponding information outputs of the first group of the device, the error selector whose information inputs are connected to the corresponding outputs of the memory unit, the synchronous input is connected to the output of the second element AND, the setup input is connected to the counter overflow output, and the outputs are to the corresponding inputs of the first decoder and are corresponding to the information outputs of the second group of the device, the second register, the information inputs of which are the corresponding inputs of the second group of the device, the sync input, the second synchronization input of the device, and the outputs are connected to the first inputs of the corresponding OR elements, the second inputs of which are connected to the corresponding information outputs of the counter, information input of which is connected to the output of the first element And, the second input of which is connected to the output of the second delay element, and the fifth delay element, input D of which is connected to the output of the second element I, and the output to the installation inputs of the first and second registers, the memory block and the counter. 58 FIG. I Fig.Z 1 A Sigma / g inlet 47 2 At Cyyod delay element 16 well The delay element 17 Jfjyyj At the exit of the nose of the nose of the counter 6 The output of the delay element 18 I At the output, & “Element, g delay 19 | At the exit s delay element 20i Fy t