SU1432611A1 - Memory with error correction - Google Patents

Abstract

The invention relates to computing and can be used as a memory device of increased reliability. The purpose of the invention is to increase the speed and reliability of the device. The device contains a memory block 1, a coding block 2, a register 3 numbers, an information corrector 4, a multiplexer 5, a synchronizer 6, a correction control block 8, and an error signal generator 9, the device eliminates loss of time for correcting information when read correctly, and also has the ability to access control for additional corrective information. 3 il. SL

Description

The invention relates to computing and can be used as a device of increased reliability.

The purpose of the invention is to increase the speed and reliability of the device.

FIG. 1 shows a block diagram of a memory device with error correction; in fig. 2 - structures on the circuit of the error signal generator; in fig. 3 is a block diagram of a correction control unit.

The device contains (Fig. 1) memory block 1, coding block 2, register 3 numbers, information corrector 4, multiplexer 5, synchronizer 6, states from block 7 (delays and matching block 1, correction control block 8, and shaper 9 signal - a lot of mistakes.

The shaper 9 contains (figure 2) elements AND NOT 10 and 11.

Correction control unit 8 contains (FIG. 3) an element NOT 12, elements AND 13 and 14, an element AND 15 and an element OR 16.

The device works as follows.

In the recording mode, the address of the memory cell, which is used to record the code of the number arriving at

information inputs of block 1 and the inputs of block 2. Block 2 generates additional digits of the number (correction code) in accordance with the selected correction code (correction code) and supplies them to the control inputs of block 1. To the input of the sample of block 1, a control signal is output from the output block 6 „

In read mode, the number code read from block 1 and the correcting code are entered into register 3. From register 3, the number code goes to the inputs of the corrector 4. As a result of the analysis of the information received from register 3, the corrector 4 can correct information about the presence of an error, In the absence of an error, the correction of information is blocked and Information is formed at the outputs of corrector 4, regardless of the analysis of a possible failure, and earlier than in the event of an error.

From the outputs of the corrector 4, information is fed to the inputs of the multiplexer, to the other inputs of which is fed

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correction code from the outputs of register 3,

Together with output information established at the output of multiplexer 5, the output of the device information must be accompanied by a tracking signal, the arrival time of the second determines the sampling time of the device, i.e. speed. This signal, accompanied by the presence and absence of correction, is produced at different times, i.e. in the absence of an error in the device, the tracking signal is generated earlier than when correction is necessary.

If there is no error in the read information, the input potential of the AND-15 unit of block 8 is fed to the control potential from the output of the equalizer 4. To the other input of the element. AND-NOT 15 when operating in the correction mode, the control potential to the input correction. As a result, a high potential arrives at the element NOT 12, which blocks the correction of information by supplying a low potential to the input of the corrector 4. In this case, when sodit resolving potential at the input of the first element And 13, to another input of which comes a signal from the synchronizer 6. The signal from the output of the element And 13 enters the input of the element OR NOT 16 and further to the output of the device. This signal serves as a signal to accompany the read information.

If there is an error, i.e. if correction is necessary, the control potential from the output of the corrector 4 is supplied to the AND-NOT 15 element. Due to this, the tracking signal from the synchronizer 6 passes to the output of the device through the AND 14 element and the OR-NOT 16 element with some delay, which is predetermined and determined e- with the necessary time for correction.

In order to preserve the ability to expose double errors, the formation of a symptom of a malfunction in the device is organized as follows. The inputs of the element AND-NOT 10 from the outputs of the corrector 4 are fed with the correction syndrome in the reverse code. In the absence of an error in the read information from the output of the element AND-NOT 10, the permitting potential enters the input of the element AND-NE 11, and in the presence of a single or double error, the resolving potential. If a

In this case, a signal is sent to the input of the second element IS-NOT 11 from the output of the corrector 4, and from the output of the element IS-NOT 11 the signal is output to the device. The presence of an error is a sign of a malfunction.

To provide diagnostics and increase reliability, the device provides access to additional correction information stored in block 1 without using additional output links. For this, a signal to block information input to multiplexer 5 comes from the control input of the device. by which the output of the main information from multiplexer 5 is blocked and the correction code of the incoming to the inputs of multiplexer 5 from the outputs of register 3 is allowed.

Claims (1)

Invention Formula A memory device with offset-days of errors, containing a memory block, a coding block, a number register, an information corrector, the information inputs of the memory block and the inputs of the coding block are connected in series and are the information inputs of the device, the outputs of the coding block are connected to the control inputs of the memory block, the address inputs and the write / read input of the memory block are respectively the address inputs and the input for setting the operating mode of the device, the information and control outputs of the memory block are connected respectively relevant to the inputs of information and check bits of the register of the number, the outputs of the information and check bits of which are connected respectively with the information and five 26 IQ 15 0 5 o five 0 eleven control inputs of the information corrector, characterized in that, in order to improve the speed and reliability of the device, a synchronizer, a multiplexer, a correction control unit and an error signal generator, the output of which is a device error output, are introduced into it, the information inputs of the first and second groups of the multiplexer connected respectively to the outputs of the control bits of the register of the number and to the information outputs of the information corrector, the control of the input and outputs of the multiplexer are the corresponding Actually, the read enable input and information outputs of the device, the synchronizer input is the device access input, the first to fourth synchronizer outputs are connected respectively to the memory input of the memory block, to the receive input of the number register, to the first and second control inputs of the correction control block, the input The correction resolution of the correction control block is the corresponding input of the device, the input of the correction block of the correction control block and the input of the error signal conditioner are connected with the output No information corrector information error, the corrector control outputs are connected to the error signal generator group, the information corrector synchronization input is a device clock input, the first input of the correction control unit is connected to the input of the information corrector correction lock, the second output of the correction control unit is an output device information. From % .f Oml 12 Omit 15 From 6 Kl4 ABOUT f3 P j J sixteen