SU1550626A1 - Code correction device - Google Patents

Abstract

The invention relates to computing and receiving discrete messages and can be used for correction by correcting the threshold level of receiving codes with structural redundancy. The purpose of the invention is to increase the functionality by correcting errors of the codes with structural redundancy. The device contains a register 1, a group of counters 2, elements AND 4.1 - 4.3, an element OR 4.4 and a control block 9 with corresponding connections. The device can be used in any data transmission systems that use structural redundancy codes with the ability to determine the nature of the error (0 - 1) or (1 - 0). 1 il.

Description

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The invention relates to computing and receiving discrete messages and can be used to correct the errors of structural redundancy codes.

The aim of the invention is to enhance the functionality by correcting the errors of structural redundancy codes.

The drawing shows a diagram of the device for the correction codes.

The device contains a register 1 group of counters 2.1, ..., 2.n (n is the number of bits in the code), a group of information inputs 3 of the device, first to third elements AND 4.1–4.3, OR 4.4, start 5 input devices, a clock input 6 of the device, a control output 7 of the device, an information output 8 of the device and a control block 9

The control unit 9 can be implemented depending on the type of the redundancy code and is intended to determine the nature of the error (1)) or (1 - 0) and output a signal at the corresponding control outputs. Register 1 is used as the input register of the control unit. 9. Counters 2.1-2.P are designed to record in them the level of the O or 1 elementary signal received from the input of the elementary signal O or 1 for a code combination in the parallel code (level). The output of the estimator is in a unit state if the counter contains a combination corresponding to the level received above the receive threshold, otherwise the output is in the zero state.

Element And 4.3 generates a signal at the control output 7, if two elements of And 4.1 and 4.2 work at once, i.e. when the combination of the proposed correction method is unrecoverable.

The device works as follows.

When receiving, with input 3, a code combination of a code with a structural backbone, the level of each elementary parcel of a code O or 1 is recorded in the corresponding counter. After recording the levels, input 5 is applied. a single potential opening elements And 4.1 and 4.2, if the block 9 control shows the nature of the error () or ().

If the nature of the error (), then the state of the counters 2.1-2.P increases until the control unit 9 stops issuing the error type (), with each next pulse, the passed AND 4.1 element and the OR 4.4 element will reset the register 1 to the initial state. When issuing an error (), the device works in the same way, only when this happens, the contents of the counters 2.1-2.P are reduced by means of the target through the AND 4.2 element.

When issuing errors () and () at the same time, the combination of a code is incorrigible and is subject to further processing or deletion.

After the control unit 9 generates zero potentials at both outputs () and (), elements 4.1 and 4.2 are closed and the code combination is read from register 1 through output 8.

The device can be used in any data transmission systems that use structurally redundant codes with the ability to determine the nature of the error () or (1 ()).

Claims (1)

Invention Formula A device for correcting codes containing a register, a group of counters and the first element I, and the outputs of the counters of the group are connected to the installation inputs of the register bits, the start input and the clock input of the device are connected respectively to the first and second inputs of the first AND element, characterized in that , in order to extend the functionality by correcting the errors of the codes with structural redundancy, it contains the second and third elements AND, the OR element and the control unit, moreover, the group of information inputs of the device with dinene with the installation inputs of the corresponding group counters, the outputs of the register bits are information output device and connected respectively to the corresponding inputs of the control unit, the first and second control outputs of which are connected respectively to the third output of the first element And and the first input of the second element And, the second and the third inputs of which are connected respectively with the clock input and with the start output of the device, the output of the first element And 51 b0626 connected to the first inputs of the third and the OR element, with the subtracting inputs of the AND element and the OR element, with the summing of the group- counters, the output of the element OR of the counters of the group, connected to the reset input of the register, the second element AND And it is the second inputs of the third element And with the control output of the device.