SU1661840A1 - Memory with self-testing - Google Patents

Abstract

The invention relates to computing and can be used in storage devices. The aim of the invention is to increase reliability by controlling error correction circuits during operation. The memory device contains a drive, registers of information and check bits, an encoder, a modulo-two adder, a decoder, the first and second OR elements, a trigger, and a control unit. The purpose of the invention is achieved by the fact that in case of detection of an error in the information or check bits, it is corrected and the syndrome is recalculated. If the syndrome is not zero, then a correction circuit error is detected on the trigger. 1 tab., 2 Il.

Description

The invention relates to computing and can be used in storage devices.

The aim of the invention is to improve the reliability of the device by monitoring the error correction circuits during operation.

FIG. 1 shows a block diagram of a self-monitoring storage device; in fig. 2 - control unit.

The device (Fig. 1) contains the encoder 1, the adder 2 modulo two, the decoder 3, the drive 4, the register 5 data bits, the first element OR 6, the second element OR 7, the trigger 8, the register 9 control bits, block 10 control .

FIG. 1 also denotes outputs 11 and 12, input 13 and output 14 of control unit 10.

The control unit 10 (FIG. 2) comprises a pulse generator 15, a counter 16, a decoder 17, a trigger 18, and an element 19.

Figure 1 also shows the access input 20, the information outputs 21, and the output 22 of a sign of a device error.

The device works as follows.

In the absence of a reference signal at input 20, registers 5 and 9, trigger 8 and counter 15 are in the zero state, and the generation of pulses by the generator 15 is also prohibited.

The device uses codes that detect single and double, as well as correcting single errors (for example, Hamming code).

When a reversal signal arrives at the input 20 of the device, a pulse generator 15 and a distributor, built on the counter 16 and the decoder 17, start for ON

00

ABOUT

It reads the time diagram of the device operation.

In read mode, the signal from output 11 of block 10 reads from accumulator 4 information bits are taken to register 5, and check bits to register 9. In encoder 1, information bits are encoded, and in adder 2, the received bits are compared. code with the contents of the register 9. On one outputs of the adder 2, the result of checking the Hamming code is output, and on the other output, the result of checking the contents of the registers 5 and 9 for parity. According to the states of output of element 6 and output of adder 2 given in the table, the presence or absence of single or binary errors is determined. Moreover, if there is a single error at the outputs of adder 2, an error syndrome appears, which enters the input of the decoder 3, and on the other output - a logical signal 1st.

By the signal from the second output of the decoder 17, the trigger 18 is set to one and the signal from the third output of the decoder allows the decoder 3 to correct the information on register 5 or 9. After correct correction, the outputs of the adder 2 should be set to logic O, and if there is no correction or incorrect correction - other combinations of values given in the table. If the correction is made correctly, then the signal from the output 14 of the decoder 17 to the trigger 8 will receive a logical O signal, and if it is incorrect, the logical 1, which is the error signal of the correction circuits.

Thus, the device used for any type of storage device allows monitoring the operation of correction circuits during the operation of the storage device, detecting any error.

Claims (1)

Invention Formula A self-monitoring memory device containing a trigger, the output of which is the output of the device error sign, the accumulator, the outputs of the first group of which are connected to the information inputs of the register of information bits, the outputs of which are the information outputs of the device and connected to the inputs of the encoder, the outputs of which are connected to the inputs of the first group of the modulo two, the outputs of the group connected to the inputs of the first OR element and to the code inputs of the decoder, the outputs of the first group of which are connected to the corresponding inverting inputs of the register of information bits rows, data inputs of the control register bits are connected to the outputs of the second group modulo two adder, characterized in that, in order to increase reliability by control circuits cor- rektsiioshibokvovrem the second OR element and the control unit are entered into the device, the first synchronized output of the control unit is connected to the synchronous inputs of the information bits register and the control bits register, the installation inputs of which are connected to the trigger setup input, the control unit start input, and the second the sync output of the control unit is connected to the sync input of the trigger, whose information input is connected to the output of the second OR element. the first input of which is connected to the output of the first OR element, and the second input is connected to the output of the modulo-two adder and to the input of the error indicator of the control unit, the output of the correction enable resolution of which is connected to the control input of the decoder, the outputs of the second group of which are connected to the corresponding inverting inputs of the control register bits FIG. 2