SU1374284A1 - Self-check storage - Google Patents

Abstract

The invention relates to computing, in particular to memory devices with error correction. The aim of the invention is to increase the reliability of the device. The device contains a drive 1, input 2 and output 3 registers, three switches 4.5 and 6, a Hamming code generator 7, a parity flag generator 8, a parity data control block 9, a comparison block 10, an OR element 11, a HE element 12, the elements And 13, block I4 control, block 15 data output, the first 16 and second 18 groups of modulo-two adders, the first 17, and the second 17 sum

Description

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Matora modulo two and a decoder 19, which transforms the code of the bit number in which the error occurred. The device can operate in two modes defined by the signals at the installation inputs 23 and 23J of the control unit 14. In the first mode, the recording of information on the inputs 21 is performed in several cycles, and the reading in one cycle, in the second mode, the recording is executed in one cycle, and the reading - in several cycles. The device provides detection and correction of one-time and two-time errors caused by systematic failures and failures, thereby increasing its reliability. In the process of recording information formiro1

The invention relates to computing, in particular to memory devices with error correction.

The aim of the invention is to increase the reliability of the device.

Figure 1 shows the functional diagram of the device; in fig. 2 - functional block diagram.

The device contains (Fig. 1) on the coder 1, input 2 and output 3 registers, first 4, second 5 and third 6 switches, Hamming code generator 7, parity characteristic generator 8, parity data control unit 9, comparison unit 10, element OR 11, elements NOT 12, elements AND 13, control block 14, data output block 15, first group of adders 16 modulo two, first 17Y and second 17 modulo-two adders, second group of adders 18 modulo two, and decoder 19.

In Fig. 1, the address inputs 20, the information inputs 21 and the outputs 22, the inputs 23 and 23j of the operation mode setting, the control input 24 are indicated. By using the device, the input 25 allows the recording of the inverse word to be written, the first 26 and second 27 inputs of the error indication.

The driver 7 generates the check bits of the Hamming code, and the driver 8 generates a parity attribute that is written to the drive 1 along with the data. When reading, the data is checked for parity in block 9 and the control code is generated by adders 16. Adders 17 are designed to correct word bits containing signs of the mode of operation and the code (direct or inverse) of the data record. This 18 allows to correct the error in the data discharge. The data is also corrected by writing the inverse information to the drive 1 after the test reading. 2 nl.

The input 28 of the sign of changing the operation mode, the input 29 of the code of the data recording code and the first through fourteenth outputs .30-43 of the control unit 14.

The control unit 14 contains (FIG. 2) delay elements 44-53, elements AND 54-62, elements OR 63-72, element OR-NE 73, RS-flip-flops 74-76, decoders 77 and 78.

The device works as follows.

Data can be written and read in two modes of operation, different; so that in the first mode of operation, the recording is performed in several cycles, and the reading in one cycle, and the errors caused by defects and faults are corrected, and in the second mode of operation, the recording is performed in one cycle, and the data is read in several cycles in the presence of errors, caused by erasures and faults. The mode of operation is determined by the polarity of the signal at inputs 23, and 23j.

In the first mode of operation, a single signal at the direct input 23, the trigger 74 (Fig. 2) is set to one and the formation of the Ready signal at the output 30 ceases. Binary code word

under the influence of the signal from the output 33 of the block 14 is transmitted through the switch 4 (Fig. 1) to the register 2, where the check bits generated by the formers 7 and 8 are also transmitted, a sign of the operating mode coming from the output 42 of the block 14.

In registers 3 and 2, the information is as follows.

In the zero bit there is a parity sign, in the first bit, a sign of the mode of operation (one at first, zero in the second mode of operation), in the second bit, sign of the data recording code (zero when writing data to drive 1 in forward mode). code and one in inverse code), in the following bits are recorded data and test bits of the Hamming code.

Under the influence of a signal from output 34 of block 14, the direct word code, the check bits of the Hamming code, the unit code in the first category, the total: sign of the mode of operation, the number in the second section, indicating that the information is recorded in the direct code through switch 5 are transmitted to drive I to write to the cell at the address arriving at the inputs 20. Then, the control reads the contents of this cell and the signal from output 31 sends the code of the word through elements 13 to register 3. In the block 10 compares the recorded and scoring codes. annogo words. If they do not match, then at input 25 a signal will be generated, through which the switch 5 will send the drive 1 to write the inverse code of the word from register 2, and the bits indicating the signs of the operation mode and the code to write the word to drive 1 will also are inverted. In this case, the information recorded in the drive 1 will be matched with the defect. At output 30, a signal is generated, allowing the next record or read to be performed. When reading a word written in the first way, the signal at input 24 of block 14 generates a signal at output 31 for which the read word is received in register 3, while output 40 of block 14 appears a constant unit potential at the input of the switch 6, which allows information from the direct outputs of the register 3 to be output to the adders 16, and the Ready signal is removed from the output 30

A random or systematic error is then corrected using adders 16, 17, 17, and 18 and a decoder 194 At the output 39 of block 14, block 15 outputs word code 22 from outputs of adders I8 to output 22, if output 28 of adder 17 shows a unit code indicating the operation mode and output 29 of the adder 17 is a zero code indicating that the information was recorded in drive 1 in the forward code. If code 3 is output from input 28 and source code 29 to output 29, indicating that the information was recorded in drive 1 in the return code, then output 38 of block 14 produces a signal that allows information 15 to be output to output 22 from the outputs of the elements NO 12. At the output 30, a ready signal is generated. In this case, a single error caused by a defect can be corrected, and a single error caused by an accidental failure in any bits of the recorded word, and the read information will be issued in one measure, i.e. with the highest possible speed.

In the second operation mode, the single signal at input 23 sets the trigger 74 to the zero state and removes the Readiness signal from output 30. The binary code word is transmitted by the switch 4 to the register 2 under the influence of the output 33 of unit 14. At this, check bits are formed. Hamming code by shaper 7, code for parity by shaper 8, and in the first and second bits of register 2, zero codes are written. The written word from the direct outputs of register 2 is written to accumulator 1 at the address supplied to inputs 20. When reading a word from a signal at input 24, block 14 generates a constant signal at output 40 and a pulse signal at output 31. The read word enters register 3 In this case, a Readiness signal is not generated at output 30. Word code and parity from the direct register outputs. 3 enters block 9, in which the code of the word is controlled by parity and the result is compared with the read parity sign. With

the coincidence of the generated and read parity features at the output 26 of the block 9, a zero code is generated, indicating that the control parity of the parity features is fulfilled, and which enters the block 1A. Simultaneously, the information from the direct outputs of register 3 through the switch 6 is fed to the inputs of adders 16, which form the control sign, and if it is not zero, then through the element OR 11 to unit 14 receives a single signal at input 27.

With this mode of operation, there are four possible readout situations.

In the first situation, the control sign at the input 27 is not zero.

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a signal is generated, according to which information from the inverse outputs of register 3 is rewritten into register 2, while block 8 re-forms the parity sign. Further, signals from outputs 35 and 37 of block 14 record information at the same address into drive 1 from direct outputs of register 2, and from signals from outputs 36 and 31 read out, information from drive 1 to register 3.

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Errors caused by erasures are corrected, and the signal from output 38 of block 14 is corrected by checking the Hamming bits of a single error caused by a malfunction or uncorrected steel output 26 - code zero, investigator 2, and inverted

but the code word is double error.

In the second situation, the sign at input 27 is not equal to zero, the sign at input 26 is equal to one (the control relation is not fulfilled), therefore there is a single error in the codeword, which is corrected by the Hamming code.

In the third situation, the sign at input 27 is zero. The sign at input 26 is zero — there are no errors in the code layer.

In the fourth situation, the sign at the input 27 is zero, there is one at the input 26, therefore in the code word there is a triple or even larger, but odd multiplicity error, which is not corrected.

In the second and third situations, the corresponding 1e codes from block 9 and the element OR 11 are fed to block 14 to a decoder 77, with which the signal at output 39 is fed to block 15, which outputs

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40

information from the output of the elements NOT V2 through block 15 to the outputs 22. At the same time, output signal 30 forms the Ready signal. Thus, in the second mode of operation, a double error will be corrected, caused by erasures and failure in one discharge of drive 1, and the information will be recorded in one cycle, i.e. with the highest possible speed.

Claims (1)

Formula isotopic A self-monitoring memory device containing a drive, a control unit, first and second switches, input and output registers, a parity indicator generator, a comparison unit, a parity data control unit, AND elements and a data output unit whose outputs are information outputs of the device, output readiness signal which at output 22, the correct code TLV is the first output of the control unit, and the Ready signal is generated at output 30. In the fourth situation, error correction is not possible, so a signal is generated at the output 43. In the first situation, when a double error is caused either by erasing in two bits of the cell of accumulator 1, or erasing in one bit and failure in the other, the correction is performed as follows. A zero signal is applied to the input 26, and a single signal is fed to the input 27, resulting in the output 32 of the block 14 50 55 The outputs of the first switch are connected to the data inputs of the input register and the inputs of the parity feature generator, the output of which is connected to the bit of the parity control of the input register, the forward and inverse outputs of which are connected respectively to the same data inputs of the second switch and the comparison unit and other data inputs of the second switch, the outputs of which are connected to the information inputs of the storage device, the information outputs of which are connected to the first input five a signal is generated, according to which information from the inverse outputs of register 3 is rewritten into register 2, while block 8 re-forms the parity sign. Further, signals from outputs 35 and 37 of block 14 record information at the same address into drive 1 from direct outputs of register 2, and from signals from outputs 36 and 31 read out, information from drive 1 to register 3. h Errors caused by erasures are corrected, and the signal from output 38 of block 14 is corrected by checking the Hamming bits of a single error caused by a malfunction or uncorrected wiping and inverted 25 thirty 35 40 information from the output of the elements NOT V2 through block 15 to the outputs 22. At the same time, output signal 30 forms the Ready signal. Thus, in the second mode of operation, a double error will be corrected, caused by erasures and failure in one discharge of drive 1, and the information will be recorded in one cycle, i.e. with the highest possible speed. Formula isotopic A self-monitoring memory device containing a drive, a control unit, first and second switches, input and output registers, a parity indicator generator, a comparison unit, a parity data control unit, AND elements and a data output unit whose outputs are information outputs of the device, output readiness signal which 0 five The outputs of the first switch are connected to the data inputs of the input register and the inputs of the parity feature generator, the output of which is connected to the bit of the parity control of the input register, the forward and inverse outputs of which are connected respectively to the same data inputs of the second switch and the comparison unit and other data inputs of the second switch, the outputs of which are connected to the information inputs of the storage device, the information outputs of which are connected to the first inputs of the AND elements, the second inputs of which are The second output of the control unit, the outputs of the AND elements are connected to the inputs of the output register, the direct outputs and the output of the parity check bit of which are connected to the inputs of the parity data control block and other inputs of the comparison block whose output is connected to the resolution input of the inverse word recording the control unit, the inputs from the third to the sixth of which are connected respectively with the control inputs of the first and second switches, the seventh and eighth outputs of the control unit are connected respectively to the input inputs si and reads of the accumulator, whose address inputs are device address inputs, the control inputs of the data output unit are connected to the ninth and tenth outputs of the control unit, the first and second inputs of which operation mode are the same name as the device inputs, the read control input of the control unit is the device of the same name, characterized in that, in order to increase the reliability of the device, the Hamming code generator, the first and second modulo two, the first and the second group sum are entered into it modulo two, a decoder, a third switch, NOT elements and an OR element, the inputs of the Hamming code generator and the data inputs of the first group of the first switch are information inputs of the device, the outputs of the Hamming code generator are connected to the data inputs of the second group of the first switch, output and output registers connected to the data inputs of the third switch, the control inputs and outputs of which are connected respectively to the eleventh and twelfth outputs of the control unit and the inputs of modulo-two two first group, the outputs of which are connected to the inputs of the WIT element and the decoder inputs, the outputs of the first and second bits of which are connected respectively with the first inputs of the first and second modulators two, the second inputs of which are connected respectively 5 to the direct outputs of the first and second bits of the output register; the outputs of the bits from the third to the last are connected to the first inputs of modulators two second groups, 0 the second inputs and outputs of which are connected respectively to the outputs of bits from the third to the last decoder and to the inputs of elements 1 Е and one of the information inputs of the data output unit, the other information inputs of which are connected to the outputs of the elements NOT, the outputs of the control unit da- parity and the element OR are connected respectively to the first and Q to the second inputs of the error indication of the control unit, the input of the indication of the changed operation mode and the input of the indication of the data recording code of which are connected co. responsibly with the outputs of the first and second modulo-two adders, the inverse outputs of the output register are connected to the data inputs of the third group of the first switch, whose data input is connected to the thirteenth Q is the output of the control unit, the fourteenth output of which is the output of a sign of uncorrectable device error. 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