SU1203364A1 - On-line storage with data correction - Google Patents

Description

1203364

gistra of commands, input of the register entry of the register of the control error indicator and the input of the initial yes.

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The invention relates to a computational technique, in particular to memory devices.

The purpose of the invention is to increase the reliability of the device.

FIG. 1 shows a functional diagram of the proposed device} in FIG. 2 and 3, respectively, functional diagrams of the most preferred embodiments of the control unit and the correction unit.

The proposed device contains (FIG. 1) the main 1 and control 2 drives, the control unit 3, the decoder 4, the correction unit 5, the element OR-AND 6, the command register 7, the AND element 8, the data register 9, the first adder 10 modulo two , the control code register 11, the switch 12, the second modulo-two adder 13 and the error flag register 14.

FIG. 1 denotes address inputs 15, information inputs and outputs 16, one of the control inputs 17, control outputs 18-21 and other control inputs 22 and 23 of the device, inputs and outputs 24 and inputs 25 of the correction unit 5, outputs 26 and 27 of the register 7 commands. Inputs 17, 22 and 23 are designed to give signals to control the recording, reading and initial installation of the device, respectively. Control unit 3 contains (FIG. 2) adders 28 and 29 and AND 30 element. Each of the bits of correction unit 5 contains. (fig.Z) element (UNEQUALITY 31 and shapers 32 and 33 signals.

The proposed device works as follows.

Depending on the two-digit code entered in register 7, the device operates either in the basic mode, or in the diagnostic mode, or in the single-error correction mode.

If there are zero levels at the outputs of register 7, the device operates in the main mode. When reading the input of register 7, there is a zero level. Input 15 receives the address, in accordance with

which, in drives 1 and 2, the corresponding memory locations are selected. Data from drives 1 and 2 are fed to the inputs of block 3. At the same time, data word j comes from drive 1

and from accumulator 2, the Hamming control code generated for a given data word when written. Block 3 generates an error sign code. At the same time, the zero code of the error sign corresponds to the absence of an error. In case the error has an odd multiplicity (, ..), an output signal is generated at output 18, received as c modulo TyiMa. DBV

of all bits of accumulators 1 and 2. In the case of an error with even multiplicity (4.,.) with the presence of: and on the direct inputs of the element OR-B a non-zero error sign code on the test 19

a signal is generated. The error sign code also goes to the inputs of the decoder 4, however, since the control input of the decoder 4 comes from the output of the And 8 element, the zero level, the decoder 4 does not generate correction signals. In this case, the data from the outputs of accumulator 1 are transmitted to inputs 24 without correction, since to input 1 1 25 of block 5

lie, correction signals are received, and at input 17 there is a zero level, switching block 5 to 15 sending data to outputs 16. When writing to the inputs 15 to the post: a is the address,

picking the required memory location. At the inputs of 16 receives the data word. At the time of setting the address, input level 17 is zero. Data word with control

code from drives 1 and 2 is fed to the inputs of the register 19. On the leading edge of the write pulse at input 1 7, register 19 is fixed by the body3

in the data stored in the selected memory cell, with its control code. Block 5, by the signal at input 17, switches to transmitting the data word from inputs 16. The recording signal at input 17 switches drives 1 and 2 to recording mode. The data word is entered into the selected cell of accumulator 1, and also enters one of the inputs of block 3, the other inputs of which receive a zero code from the outputs of accumulator 2. At the same time, block 3 generates a Hamming control code written to the accumulator 2. The control code generated in this way, together with the data word, they go to the first and second groups of inputs of the adder 10, the third group of inputs of which from the outputs of register 9 receives the data word with the control code stored in the selected cells of accumulator 1 until the signal arrives a record, and the fourth group of inputs of the adder 10 receives the common control code from the outputs of register 11. During the recording signal at input 17, the adder 10 generates a new value of the general control code, which is on the falling edge of the recording signal at input 17 - in register 11. This completes the write cycle.

To switch the device to the single error correction mode, the code 7 is entered into the register 7 with a single value at output 26. From the output of the AND 8 element to the input of the decoder 4, a single level arrives. When recording in this mode, the device functions similarly to the main mode. When reading, the error symptom code generated by block 3 is fed to the inputs of the decoder 4. If the error code is not zero, then the decoder 4 at one of its outputs generates a correction signal that arrives at the corresponding bit of input 25 of block 5 which, when transmitting data to outputs 16, inverts information in the specified bit, and this is the one-time error correction. Otherwise, the device functions in the same way as in the main mode, while at the outputs 18 and 19 there are generated error signals about the presence of errors, and signals of odd errors can be ignored03364

c, since the correction of single, therefore odd errors. In diagnostics mode, the device switches when a code with a single level at output 27 arrives at the input of switch 12 enters into register 7. Before switching to diagnostics mode, switch 12 transmits a common control code from the outputs of register 12 to the information inputs of register 14. Before the start of diagnostics, the common control code was rewritten into register 14, which is) 5) exists on the falling edge of the signal at input 22. Therefore, the last operation before switching to the diagnostic mode should be the read operation. Thus, after switching to diagnostic mode in register 14, there is a control code, and switch 12, using a signal at input 27, connects outputs of adder 3 to register 14 inputs. After this, to perform diagnostics, it is necessary to interrogate in read mode all cells of the device arbitrary sequence.

To interrogate each memory cell, its address is fed to inputs 15, and a single read signal to input 22. For a given address from the accumulator 1, the data word is extracted, from accumulator 2 the control code, which is fed to the inputs of the adder 13, is

35, the other inputs of which receive the current code value from the outputs of register 14. From the output of adder 13, the modulo sum of these two codes goes through switch 12 to the inputs of register 14 and is written to it at the falling edge of the signal at input 22. If the next read data word or its the control code contains a detectable error, then block 3 generates a non-zero error symptom code, and at one of the outputs 18 and 19 there appears a warning signal about the presence of an error. In this case, the device is counted as a word.

50 data on outputs 16 and the control code from outputs 20. Upon completion of the survey of all memory cells in register 14, a common code of the total error symptom will be generated,

55 which can be read from the outputs 21, the zero value of which indicates the presence in the data of one or a group of errors. Thus, in pro30

five

During the interrogation process, the device provides the following diagnostic information: all the corrupted data words with their control codes and, the total code of the error sign, which allows correcting a wide class of errors of various multiplicity with a high degree of confidence. Error correction is carried out in software and is assigned to the appropriate computer operating system program in which the proposed device is used.

If there is an error in only one word, it is necessary to add together the modulo two specified word and the summary code of the syndrome. For the code obtained, the Hamming code of the syndrome should be calculated. If it is zero, the error is corrected correctly. If there are errors in a few words, it is necessary to consider several options / 5

033646

localization of erroneous bits in data words and control codes. In this case, first of all, the bits of the data to which J indicate single unit digits in the summary code of the syndrome are inverted. After each change in a given word, its syndrome is checked for equality to zero. Thus, the search and correction of errors consists in such a minimal change in the erroneous words in the data, in which the syndromes of all these words and the total syndrome are eliminated.

15 When the device operates in the diagnostic mode, error correction by block 5 is blocked by a single level at the inverse of the input element of AND 8, the initial installation is performed by writing 20 zero codes of all memory cells, after which a signal is sent to the input 23, which ynush; 11 register.

FIG.

20

Claims (1)

OPERATIVE MEMORY DEVICE WITH INFORMATION CORRECTION, containing the main and control drives, the control unit, the outputs of which are connected to the information inputs of the control drive and decoder, the outputs of which are connected to one of the control inputs of the correction unit, one of the inputs and outputs of which are connected respectively with the outputs of the main drive and with information inputs of the main drive and one of the inputs of the control unit, the other inputs of which are connected to the outputs of the control drive, others the moves and outputs of the correction block are information inputs and outputs of the device, characterized in that, in order to increase the reliability of the device, modulo two adders, a switch, a command register, a data register, a control code register, an error sign register, an OR element are introduced into it And the element And, moreover, the inputs of the first group of the first adder modulo two are connected to the outputs of the control unit, the inputs of the first group of the second adder modulo two and the data register are connected to the outputs of the control drive, the outputs of the main The capacitor is connected to the inputs of the second group of adders modulo two and a data register, the outputs of which are connected to the inputs of the third group of the first adder modulo two, the outputs and inputs of the fourth group of which are connected respectively to the inputs and outputs of the control code register and one of the inputs of the switch, the outputs of which connected to the inputs of the error symptom register, the outputs of which are connected to the inputs of the third group of the second adder modulo two, the outputs of which are connected to other inputs of the switch, the outputs of the com register nd are connected respectively with the direct input of element II and with the control input of the switch and the inverse input of the element And whose output is connected to the control input of the switch, the direct inputs of the element OR-AND are connected to one of the outputs of the control unit, the other output of which is connected to the inverse input of the element OR -And the output of which and the other output of the control unit are respectively the outputs of the even and odd error signals of the device, the control outputs of which are the outputs of the error sign register and the control accumulator one of the control inputs of the device are the entries of the data register, the register of the control code of the drives, the control unit and the other control input of the correction unit, the other control inputs of the device 1203364. The inputs of the command histogram re1203364, the input of the register register for setting the register of the error control sign, and the input of the initial yes are, respectively.