JP2906850B2 - Time-division switch monitoring circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division switch monitoring circuit, and more particularly to a time-division switch in which time slot data in an input data signal is switched one-to-one with time slot data in an output data signal. And a time-division switch monitoring circuit.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional time-division switch monitoring circuit. Input data signal 101
A parity generation circuit 102 which receives an input data signal 101, an input parity signal 103, and a frame pulse signal 109 and outputs an output data signal 105 and an output parity signal 106. Switch 104 and output data signal 10
5 and a parity detection circuit 107 which receives the output parity signal 106 as an input and outputs a parity error output signal 108. The parity calculation result on the input side is passed to the time division switch 104 together with the data signal. Error detection has been performed by performing a parity operation and comparing.

[0003]

In the conventional time-division switch monitoring circuit based on parity detection, it is not possible to confirm that data is not normally switched in the time-division switch, for example, writing data twice or forgetting to write data. was there.

[0004]

SUMMARY OF THE INVENTION A time division switch monitoring circuit according to the present invention includes an insertion unit for inserting a parity signal into a time division switch, and detects a parity error in an output signal of the time division switch. A detection unit, wherein the insertion unit inverts the parity signal for any N time slots in the input frame and inputs the inverted parity signal to the time division switch, and the detection unit outputs the output of the time division switch. It is characterized in that it is determined whether or not the number of parity signals of the signal is N in a frame.

The insertion section includes a parity generation circuit that receives an input data signal and outputs an input parity signal, and a parity inversion circuit that receives the input parity signal and a frame pulse signal and outputs a parity inverted signal. The time division switch receives the input data signal, the parity inversion signal, and the frame pulse signal as input, outputs an output data signal and an output parity signal, and the detection unit outputs the output data signal and the output parity signal. A parity detection circuit that receives the parity error output signal as an input and outputs the parity error output signal and the frame pulse signal and outputs an error output signal;

[0006]

The time division type switch monitoring circuit according to the present invention, when the time slot data in the input data signal of the time division type switch is switched on a one-to-one basis with the time slot data in the output data signal, is used in the insertion section. A parity inverting circuit is added to any N (N is a natural number) time slots in a frame, and a parity operation result of specific time slot data is input to a time division switch as a monitoring signal. Then, the detection unit checks the error by inputting the output parity signal, which is the output of the time division switch, to the parity detection circuit and determines whether or not there are N errors. The parity counting circuit determines that there is no error when there are N errors, and that there is an error when it is not N. Further, the parity inversion circuit of the insertion unit changes the inversion position in the frame for each frame, and checks all time slots in the frame.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a time-division switch monitoring circuit according to the present invention, and FIG. 2 is a timing chart of the present embodiment.

In this embodiment, time-division switch inputs 1 to 1 are used.
Parity error (position surrounded by circle A) occurs in the data of the second frame after inputting and outputting a total of six frames of the sixth frame, and in the output fifth frame, certain time slot data (position surrounded by circle B) Is detected as an example.

In FIG. 2, six arrows indicated by C indicate the positions of the time slot data with the parity inverted.
The six arrows indicated by D indicate the positions where the time slot data with the parity inverted is switched.

The embodiment shown in FIG. 1 is obtained by adding a parity inverting circuit 201 and a parity counting circuit 203 to the conventional example shown in FIG. The parity inverting circuit 201 receives the parity input signal 103 as input, and inverts the parity of any one time slot data for each frame. The inversion position is changed for each frame, and is performed for all time slots. The parity counting circuit 203 receives the parity error output signal 108 as input and determines whether or not the number of parity errors is one for each frame. If the number of parity errors is one, there is no error.
4 is output. In FIG. 2, in the output first, third, fourth, and sixth frames of the output data signal 105, there is one parity error output signal 108 for each frame, so that no error is output to the next frame. However, in the output second and fifth frames, the parity error output signal 108 is 2
Error output signal 204 in the next frame.
Is output.

[0011]

As described above, in the time division switch monitoring circuit of the present invention, the time slot data in the input data signal of the time division switch is switched one-to-one with the time slot data in the output data signal. In such a case, it is possible to detect that the switch was not switched normally, such as writing or forgetting to write data twice in the time division switch.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a time division type switch monitoring circuit of the present invention.

FIG. 2 is a timing chart of the present embodiment.

FIG. 3 is a block diagram illustrating an example of a conventional time-division switch monitoring circuit.

[Explanation of symbols]

 Reference Signs List 101 input data signal 102 parity generating circuit 103 input parity signal 104 time division switch 105 output data signal 106 output parity signal 107 parity detection circuit 108 parity error output signal 109 frame pulse signal 201 parity inversion circuit 202 parity inversion signal 203 parity counting circuit 204 Error output signal

Claims (2)

(57) [Claims] 1. An input unit for inserting a parity signal into a time division switch, and a detection unit for detecting a parity error of an output signal of the time division switch, wherein the insertion unit includes an arbitrary part of an input frame. For the N time slots, the parity signal is inverted and input to the time-division switch, and the detection unit determines whether the parity signal of the output signal of the time-division switch is N in a frame. A time-division switch monitoring circuit, characterized in that it determines 2. The insertion unit includes: a parity generation circuit that receives an input data signal as an input and an input parity signal as an output; and a parity inversion circuit that receives the input parity signal and a frame pulse signal and outputs a parity inverted signal. The time division switch receives the input data signal, the parity inversion signal, and the frame pulse signal as input, outputs an output data signal and an output parity signal, and the detection unit outputs the output data signal and the output parity signal. 2. A parity detecting circuit comprising: a parity detection circuit which receives a parity error output signal as an input; and a parity counting circuit which receives the parity error output signal and the frame pulse signal as inputs and outputs an error output signal. Time-division switch monitoring circuit.