JPH05100878A - Selection circuit error detection system - Google Patents

Abstract

PURPOSE:To detect the malfunction of a selection circuit with a little increase of hardware amount. CONSTITUTION:Plural data holding circuits 1 and 2 holding data including a parity, the selection circuit 6, a parity check circuit 7, the decoding circuit 3 of selection signals 10 and 12, the parity inversion control circuits 4 and 5 of the respective holding circuits 1 and 2 and an error discrimination circuit 8 inputting a control signal 11 and detecting a selection error after a parity error is detected are given. Furthermore, a decoding circuit 3 has an enable terminal. An error discrimination circuit discriminating the data parity error with the selection error is given.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a selection circuit error detection system for detecting malfunction of a selection circuit.

[0002]

2. Description of the Related Art Conventionally, as a method of detecting a malfunction of a selection circuit, there is a method of duplicating the selection circuit and comparing output values of the respective selection circuits to check whether they match.

Further, as a known example, Japanese Patent Laid-Open No. 60-1448.
No. 35 (selection circuit error detection method), a method of detecting an error from the even / odd parity of the input signal path value of the decoder circuit, which is unique to the data holding circuit of Japanese Patent Laid-Open No. 01-309137 (selection circuit malfunction detection method). There is a method of holding a discrimination value and discriminating a malfunction by the discrimination value of the output of the selection circuit.

[0004]

However, the method of detecting the malfunction of the selection circuit requires twice the hardware amount due to the duplication.

Therefore, it is an object of the present invention to provide a method for detecting a malfunction of a selection circuit without increasing the amount of hardware.

[0006]

According to the present invention, the output of any one of the data holding circuit groups for holding data including parity is selected by the selection circuit, and the output of the selection circuit is selected. In a selection circuit error detection method for performing a parity check, a decoding means for decoding a selection signal and an inverting means for inverting the parity of each of the data holding circuits are provided, and the parity of the data holding circuit that is not selected is inverted. A selection circuit error detection system characterized by detecting a selection error by the parity check when inputting to the selection circuit and outputting incorrect data of the data holding circuit due to a malfunction of the selection circuit is obtained.

Further, according to the present invention, there is provided a selection circuit error detection system characterized in that the decoding means has an enable terminal for inputting a control signal.

Further, according to the present invention, there is provided a selection circuit error detection system characterized by comprising an error discrimination means for discriminating a data parity error and a selection error by inputting the parity check result and the control signal.

[0009]

The decoding circuit inputs the selection signal and outputs the decoding result to the parity inversion control circuit. The parity inversion control circuit inverts the parity of the non-selected data holding circuit. If the selection circuit malfunctions and outputs the value of the data holding circuit that is not selected, an error occurs in the parity check circuit. In order to distinguish between the parity error of the data holding circuit and the selection error of the selection circuit, the decoding circuit inputs the control signal, and the parity inversion control circuit inverts the parity only when the selection error is determined. Further, the error discrimination circuit inputs a control signal and detects a selection error after detecting a parity error.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the selection circuit error detection system of the present invention. Referring to FIG.
The selection circuit error detection method includes a first and second data holding circuits 1 and 2 for holding data including parity, a selection circuit 6, a parity check circuit 7, and first and second selection signals 10 and 12. It has a decoding circuit 3 and first and second parity inversion control circuits 4 and 5. The first and second selection signals 10 and 12 are exactly the same signals,
The circuits that output these should be different. This is because if these signals are output from the same circuit, a failure of this circuit will cause both the first and second selection signals 10 and 12 to malfunction, and as a result,
This is because the malfunction of the selection circuit 6 cannot be detected.

When the first and second selection signals 10 and 12 are "0", the selection circuit 6 selects the first data holding circuit 1 which holds the data including the parity, and holds the first data holding. The data and parity of the circuit 1 are output. The decode circuit 3 sets the decode output 17 to “0”, and inputs the parity of the selected data holding circuit 1 to the selection circuit 6 as it is without inverting it by the first parity inversion control circuit 4 by exclusive OR. Further, the decode circuit 3 sets the decode output 18 to “1” and sets the parity of the unselected second data holding circuit 2 to the second parity inversion control circuit 5.
Is inverted and input to the selection circuit 6.

When the first and second selection signals 10 and 12 are "1", the selection circuit 6 selects the second data holding circuit 2 which holds the data including the parity, and the second data holding circuit. 2 data and parity are output. The decode circuit 3 sets the decode output 18 to “0”, and the parity of the selected second data holding circuit 2 is directly inverted to the selection circuit 6 without being inverted by the second parity inversion control circuit 5 by exclusive OR. input. Further, the decode circuit 3 sets the decode output 17 to “1”, the parity of the unselected first data holding circuit 1 is inverted by the first parity inversion control circuit 4, and is input to the selection circuit 6.

When the selection circuit 6 malfunctions, the parity output of the selection circuit 6 becomes the inverted incorrect parity of the second data holding circuit 2 which is not selected. Therefore, the parity check circuit 7 must detect the error. You can

However, in this state, the error detected by the parity check circuit 7 is the original parity error due to the failure of the selected first data holding circuit 1 or the second data circuit 2, or the failure of the selection circuit 6. The problem remains that it is not possible to distinguish between selection errors. Therefore, the decode circuit 3 is provided with an enable terminal so that the parity error detection and the selection error detection are performed separately.

When a parity error is detected, the control signal 11
Is set to "0", and the first and second parity control signals 17 and 18 of the decoding circuit 3 are all set to "0". The first and second parity inversion control circuits 4 and 5 output the parity to the selection circuit 6 without inverting it. Since the parity output of the selection circuit 6 is not inverted, the parity error detection result of the parity error detection circuit 8 becomes a parity error of the data held in each data holding circuit 1 or 2.

When a selection error is detected, the control signal 11 is set to "1", and the first and second parity inversion control signals 17 and 18 of the decoding circuit 3 are output according to the selection signal 10, respectively. The first and second parity inversion control circuits 4 and 5 are the selected first and second data holding circuits 1 and 2.
The parity of the first and second data holding times 1 and 2 which is not selected is inverted without inverting the parity of 2, and is output to the selection circuit 6. When the selection circuit 6 malfunctions and outputs the data and parity of the unselected first and second data holding circuits 1 and 2, the parity is inverted. The parity error detection result of the parity check circuit 7 becomes a selection error of the selection circuit 6.

When the first and second data holding circuits 1 and 2 are out of order, the parity check circuit 7 outputs an error when a parity error is detected and also outputs an error when a selection error is detected. Therefore, the selection error is detected after the parity error is detected. If no error occurs when a parity error is detected, a selection error is detected. If an error occurs when a parity error is detected, no selection error is detected.

An error discrimination circuit 8 is provided to make the above-mentioned error discrimination. The error discrimination circuit 8 inputs the control signal 11 in addition to the check result of the parity check circuit 7,
Parity error and selection error are discriminated and output.

[0020]

As described above, according to the selection circuit error detection method of the present invention, when data incorrectly selected by the selection circuit is output from the selection circuit, this can be detected, so that an accident such as garbled data can be prevented. Can be prevented in advance,
Furthermore, since a parity check circuit that is commonly used is used, there is an effect that the increase in the amount of hardware can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a selection circuit error detection system of the present invention.

[Explanation of symbols]

 1, 2 Data holding circuit 3 Decoding circuit 4, 5 Parity inversion control circuit 6 Selection circuit 7 Parity check circuit 8 Error determination circuit 10, 12 Selection signal 11 Control signal 13 Selection data output 14 Selection parity output 15 Parity error 16 Selection error 17 , 18 Parity inversion control signal

Claims (3)

[Claims] 1. A selection circuit error detection method in which an output of any one of the data holding circuits which holds data including parity is selected by a selection circuit, and a parity check is performed by the output of the selection circuit. , A decoding means for decoding the selection signal and an inverting means for inverting the parity of each of the data holding circuits, and inverting the parity of the data holding circuit that is not selected and inputting it to the selection circuit. A selection circuit error detection method characterized by detecting a selection error by a parity check when the circuit outputs incorrect data from the data holding circuit due to a malfunction. 2. The selection circuit error detection system according to claim 1, wherein the decoding means has an enable terminal for inputting a control signal. 3. An error discriminating means for discriminating a data parity error and a selection error by inputting the parity check result and the control signal.
Alternatively, the selection circuit error detection method described in item 2.