JPH0336634A - Fault detecting system for circuit including register file - Google Patents

Abstract

PURPOSE:To improve the resolution of a faulty range by judging the state of a read flag circuit concerning error, and identifying whether the error is generated by reading or reading/writing. CONSTITUTION:The identification for the write/read of data to plural words in a register file part 200 is executed by plural read flag circuits 210-213. A parity check circuit 240 detects the error of the data read from the file part 200. When the error is detected in the read data, the states of the circuits 210-213 are identified and the fault range of the circuit is selected. Thus, since the state of the read flag circuit is judged and it is identified whether the error is generated by reading or reading/writing when the error is detected in the read data, the fault range of the circuit including the register file can be specified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault detection method in a circuit, and more particularly to a fault detection method in a circuit including a register file.

[Background Art] In recent years, the proportion of intermittent failures in 1+I of logic circuits forming information processing devices has been increasing. For this reason, there is a fault diagnosis method in which the error output of the error detection circuit that detects intermittent faults is sent to the error indicator flag circuit, and this sent error information is indexed into a fault diagnosis dictionary to point out the suspected range of the fault. Adopted (for example,
NEC Technical Report Volume 40 No. 11 rAcos System 200
0 series RASJ).

And 5. The second fault detection method is to uniquely detect this register file and the write data generation circuit of this register file as a suspected fault area by using the error output of the error detection circuit that detects errors in the read data of the register file. It becomes.

[Problem to be Solved by the Invention 1] The above-described conventional fault detection method for a circuit including a register file is such that when read data from a register file is output as an error by an error detection circuit, this register file and this register file are not written. Since this method uniquely selects the data generation circuit as the suspected failure area, if no error is detected after reading from the register file, the normality of the data generation circuit written in the register file is confirmed. Even in the case where the data generating circuit is included in the suspected fault range, there is a problem in that the resolution of the fault range is degraded as a result.

[Means for Solving the Problems 1] In order to solve such problems, a device based on a failure detection method for a circuit including a register file according to the present invention is provided corresponding to a plurality of words in the register file section, This device includes a plurality of read flag circuits that identify writing or reading of data, and an error detection circuit that detects errors in data read from the register file section.

[Operation] When an error in read data is detected, the state of the read flag circuit is determined to identify whether the error is associated with reading or with reading and writing.

As a result, the failure range of the circuit including the register file section can be identified.

[Example] Next, the present invention will be explained with reference to the drawings.

The figure is a block diagram showing an embodiment of a failure detection method for a circuit including a register file according to the present invention.

In the figure, 10.20 is a circuit block of the minimum suspect range (minimum fault range) pointed out when a failure occurs, 30.270 is a signal line, and 100 is a circuit block that generates data to be written to the circuit block section 20. A register file input data generation circuit; 200 is a register file section into which data from the register file input data generation circuit 100 is written; 210 to 213 are register file sections 2;
1 to 1 for each of the 4 words (not shown) in 00
This is a read flag circuit provided correspondingly.

220 is a read address signal line, 225 is a write address signal line, and 230 is a read address signal line 22.
0 selects the output of one of the read flag circuits 210 to 213; 240 is a parity check circuit (error detection circuit) that performs a parity check on data when reading data from the register file section 200; 250 is an error indicator flag circuit that sets an error flag when an error is detected by the parity check circuit 240; 260 is a read flag circuit 210 to 21 that is already set when the flag of the error indicator flag circuit 250 is set and turned on;
280 is a decoder that decodes address signals from the read address signal line 220' and the write address signal line 225.

The operation of the failure detection method for a circuit including a register file subjected to tR as described above will be explained.

Data generated by the register file input generation circuit 100 is transmitted to the register file section 20 via the signal line 30.
When the write address signal is sent and written to the corresponding word in 0 (hereinafter referred to as word i), the write address signal sent from the write address signal line 225 at this time is sent to the decoder 2.
80, and based on this decoded address signal, a read flag circuit (
The read flag circuit (hereinafter referred to as the read flag circuit i) is turned off. This read flag circuit i maintains an off state until the data of the corresponding word i is read. Therefore, before the first read from word i in the register file unit 200, the read flag circuit i is in an off state.

Then, when reading is started, the own block identification flag circuit 260 has a selector 23 controlled by the read address signal from the read address signal line 220.
The read flag circuit i selected as 0 is set to the off state, that is, "0". Further, at this time, the read address signal sent from the read address signal line 220 is decoded by the decoder 280, and the read flag circuit quantity corresponding to word i is turned on based on the decoded address signal. Then, when an error is detected by the parity check circuit 240 and the error indicator flag circuit 250 is turned on when reading this word l, the own block identification flag circuit 260 outputs "O".
This “0” state is maintained by the error indicator flag circuit 250 via the signal line 270.

Next, in this state, that is, register file section 2
A case will be described in which a second read is performed before writing to 00 is performed. Before performing the second read, the read flag circuit quantity is in the on state as described above, and when the read starts, the own block identification flag circuit 260 contains the read flag selected by the selector 230. The flag circuit quantity is turned on, that is, "11" is set. Also, at this time, the read flag circuit quantity is turned on. Then, when reading this word i, an error is detected by the parity check circuit 240 and the error indicator flag is set. When the circuit 250 is turned on, the white block identification flag circuit 260 is in the "■" state.

Next, the results described above are shown in the table below.

This table shows an example of the structure of a fault diagnosis dictionary when a fault occurs in the circuit block 10.20.

According to this table, when an error occurs when reading the first indentation marked and the error indicator flag circuit 250 is on, that is, in the "1" state, if the own block identification flag circuit 260 is "0" , an error occurred either when writing or reading data.
The suspected area is circuit block section 10 and circuit block section 2.
0 is selected.

Next, if an error occurs when reading the second recess as described above, and the error indicator flag circuit 250 is on and the own block identification flag circuit 260 is rl, this means that the error occurred when reading data. Then, the circuit block section 20 is selected as the suspected range.

[Effects of the Invention] As explained above, the failure detection method for a circuit including a register file according to the present invention determines the state of the read flag circuit when an error in read data is detected, and detects the read problem. Since the configuration is configured to identify whether the error is an error associated with reading or writing, or an error associated with reading and writing, the fault range of the circuit including the register file can be identified, and the resolution of the fault range can be improved.

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment of a failure detection method for a circuit including a register file according to the present invention. 10.20...Circuit block, 30,270-...
- Signal line, 100...Register file input data generation circuit, 200... -Register file section, 210
~213... Read flag circuit, 220... Read address signal line, 225... Write address signal line, 230... Selector, 240... Parity check circuit, 250... Error indicator flag circuit, 260... own block identification flag circuit,
280... Decoder.

Claims (1)

[Scope of Claims] A circuit including a register file section consisting of a plurality of words, comprising: a plurality of read flag circuits provided corresponding to the plurality of words to identify writing or reading of data to the words; an error detection circuit that detects an error in the data read from the register file section, and when an error in the read data is detected, the state of the read flag circuit is identified and the circuit including the register file is detected. A failure detection method for a circuit including a register file, characterized in that a failure range is selected.