JPS60191350A - Memory device - Google Patents

Abstract

PURPOSE:To detect an existing fault through simple constitution by outputting a report signal showing a signal which shows the generation of an error when a signal showing the generation of a correctable error is produced. CONSTITUTION:A memory part 2 is provided together with an error detection/ correction code generating part 3, an error correction/detection code checking/ correction part 4 and an error signal switching part 5. The memory diagnosis is carried out when the system power supply is applied. In this case, an FF6 is set when a diagnosis mode is set. Then the part 5 performs control so that two error report signals 18 and 19 can be delivered. Then a memory test is carried out. Then a signal 18 showing the generation of a correctable error is outputted from the part 5 when a correctable error is produced. Thus it is possible to recognize the presence of a defective memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device, and more particularly to a memory device having an error correction function.

[Ku IJ] In order to improve the reliability of memory devices, some devices have a function to automatically correct errors when reading data. This type of device is capable of automatically correcting a 1-bit error in an l word, and only detecting an error of 2 or more bits.

However, the following problems arise because focus errors are automatically corrected. That is, even if there is a fixed 1-bit failure, the Hatatoki error is automatically corrected, so that it is impossible to recognize from the outside that a failure has occurred in the memory. If left in such a state without repair, a regular or 111% one-hit error will occur.

When this happens, an uncorrectable 2-bin I-error will result.

Therefore, a problem arises in that the entire device including the memory device no longer functions properly.

Therefore, even for errors that can be corrected, there is a method of reporting the occurrence of the error using another means such as an interrupt, and keeping a record of the address where the error occurred, the number of times it occurred, etc., but this method only detects fixed failures. Although this method is effective against intermittent failures, it has the disadvantage that the circuit configuration is complicated and the processing program is also complicated.

An object of the present invention is to provide a memory device that is capable of detecting fixed failures that can be corrected using a simple circuit and a proper program.

A memory device with a self-error correction function according to the present invention is provided with means for generating a report signal indicating the occurrence of an error when a correctable error occurs, and this report signal can be derived. Features.

J.L.J. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a memory device 1 includes a memory section 2. It consists of an error detection and correction code generation section 3, an error detection and correction code check and correction section 4, and an error signal switching section 5.

This switching section 5 is controlled by an FF (FF) 6 which is serrated according to the error diagnosis mode.

10 is a read signal, 11 is a write signal, 12 is an address signal, 13 is write data, 14 is read data after error correction, 15 is an error report signal, 16 is write data with an error detection and correction code added, 17 is read data, 18 is an error report signal indicating the occurrence of a correctable error, and 19 is an error report signal indicating the occurrence of an uncorrectable error.

FIG. 2 is a flowchart showing the operation of such a device, and when the system power is turned on, memory diagnosis is performed according to flowchart 1. At this time, when the diagnostic mode is set, FF6 is set and the signal switching section 5 outputs both of the two error report signals 18 and 19 n1.
It is controlled to a functional state. A memory test will then be conducted. Therefore, even if a correctable error occurs, the error report signal 18 indicating the occurrence of a correctable error is output from the switching unit 5. Therefore, it becomes possible to recognize the existence of a defective memory, and detailed information such as an error occurrence address can be reported by the processing program, allowing the user to recognize the existence of an underlying failure. Therefore, this inherent failure can be repaired at an early stage, and expected fatal failures can be prevented.

It should be noted that errors can occur during data reading, but they can also occur during temporary reading for partial writing, and the term "data reading" in the above description includes both of these.

According to the present invention, correctable errors are also reported as errors in the diagnostic mode, so inherent failures can be detected at an early stage with a simple circuit and a simple program. It becomes possible to detect the problem, and a fatal failure can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flow chart showing the operation of the blocks in FIG. Description of symbols of main parts 1 is a memory device, 2 is a storage section, 4 is an error check and correction section, 5 is an error signal switching section, and 6 is an FF. Applicant NEC Corporation Agent Patent Attorney Nobuo Sairo

Claims (1)

[Claims] A memory device with a self-error correction function (C), characterized in that it is provided with means for generating a report signal indicating the occurrence of an error when a correctable error occurs, and is capable of deriving this report signal. memory device.