JPS63310045A - Microcomputer - Google Patents

Abstract

PURPOSE:To allow a CPU to detect the presence of a defective cell in a memory by providing an error signal generating notice means for informing the status of occurrence of an error signal to the CPU of a microcomputer. CONSTITUTION:When data B stored in an EEPROM 2 is read by an ECC decoder 1b, the decoder 1b detects the presence of an error bit based on the code system of the data B to apply the correction and latches an error signal E to a latch circuit 6 to set an error flag F to 1. Since the error flag F is outputted to a data bus 4 in outputting the obtained data to the data bus 4, the CPU can detect there is a defective cell in an address in which the data is stored. Thus, the CPU can avoid the data from being written in the address where a defective cell exists afterwards.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique for preventing data destruction in a readable/writable memory.

[Conventional technology]

FIG. 2 is a block diagram showing a storage section of a conventional microcomputer equipped with an EEPROM.

In FIG. 2, this storage section is E for data storage.
EPROM memory section 2 and this EEPROM memory section 2
An error correction circuit 1 is provided for detecting and correcting errors in data stored in the memory. Of these, the error correction circuit 1 includes an ECC encoder 1a provided on the input side of the EEPROM 2 memory section 2, and an FCC decoder 1b provided on the output side of the EEPROM memory section 2.

Next, the error correction operation by the error correction circuit 1 will be explained.

Now, for example, 8-pit data A is being sent from data bus 4 to E.
Assuming that it is input to the CC encoder 1a, the ECC
The encoder 1a generates, for example, 12-bit data B based on the input data A. This data B is
This is data that has redundancy applied to data A based on the principle of a predetermined error correction code, and has a code system that is uniquely determined for data A, and as described later, it corrects errors in bit units. It is possible to detect and correct it. Then, data B having such redundancy with respect to data A is output to the EEPROM memory section 2 and written. However, if there is a malfunctioning memory cell (defective cell) among the memory cells of the EEPROM memory section 2 in which data B is to be stored, data C different from data B will be stored due to the influence of this defective cell. It will be remembered.

When the data C erroneously stored in the EEPROM memory section 2 in this way is read out by the ECC decoder 1b,
The ECC decoder 1b corrects the read data to correct data B by detecting the presence of error bits and correcting the error bits based on the aforementioned code system. Thereafter, data A is generated from data B by performing the reverse conversion to that of the FCC encoder 1a. This data A is then output to the data bus 4 via the data output line 5.

Note that if there is no defective cell among the memory cells within the address where data B is to be stored and data B is correctly stored in the EEPROM memory section 2, the ECC decoder 1b will not detect an error bit (i.e. , no error bits), only the conversion from data B to data 8 is performed.

As mentioned above, this microcomputer uses EEPR
An error correction circuit 1 is provided in connection with the OM memory section 2, and an E
EEP due to defective memory cell in EPROM memory section 2
Errors in data stored in the ROM memory section 2 are relieved.

[Problem that the invention seeks to solve]

However, since conventional microcomputers are configured as described above, even if the memory cell being used is a defective cell, the CPU cannot know this and cannot avoid using the defective cell. Can not. For this reason, the reliability of the memory cell deteriorates as writes are repeated.
In EEPROMs and the like, as the number of defective cells increases, the frequency of storing data in defective cells also increases, and the number of error bits included in data C increases.

If the number of error pits in data C exceeds the number of bits that can be corrected using the data B coding system, there is a problem in that the same data that was written cannot be read out and the data is destroyed. .

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a microcomputer that can avoid the use of defective cells and prevent data destruction.

[Means for solving problems]

The microcomputer of the present invention includes an error signal generation circuit that generates an error signal when an error in stored data is detected by the error correction circuit, and an error signal generation circuit that notifies the CPU of the microcomputer of the generation status of the error signal. A notification means is provided.

[Effect]

In this invention, the CPU can detect the presence of a defective cell in the memory by knowing the generation status of the error signal from the error signal generation circuit. For this reason,
This allows the CPU to avoid using defective cells and prevent data from being destroyed. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a storage section of a microcomputer that is an embodiment of the present invention.

In FIG. 1, this microcomputer differs from the conventional microcomputer (FIG. 2) in the following points. First, in the microcomputer shown in Figure 1, E
An error signal generation circuit 3 is incorporated inside the CC decoder 1b. This error signal generation circuit 3 is a circuit that generates an error signal E based on the determination result when the ECC decoder 1b determines that there is an error in the stored data (output data) of the EEPROM memory section 2. Further, a latch circuit 6 that inputs and latches the error signal E is provided at a subsequent stage of the error signal generation circuit 3. The latch output of the latch circuit 6 is applied as an error 7 lag F to the data bus 4 via the flag signal line 7. Needless to say, a CPU (not shown) is connected to the data bus 4. Therefore, the latch circuit 6 and the flag signal line 7 detect the occurrence status of the error signal E by CP.
It forms an error signal occurrence notification means for notifying U.

Next, the CPU of this microcomputer is EEPRO
The operation when detecting the presence of a defective cell in the M memory section 2 will be described.

In this microcomputer as well, data is input in the same way as in conventional microcomputers, and data A input from the data bus 4 to the FCC encoder 1a is converted to redundant data B and output to the EEPROM memory section 2. Ru.

When a defective cell exists at the address where data B is to be stored, data C, which is different from data B, is stored in the EEPROM memory section 2.

When this data C is read out to the ECC decoder 1b, E
The CC decoder 1b detects the presence of error bits based on the code system of data B and performs correction. At this time, the error signal E output from the error signal generation circuit 3
becomes active and is latched by the latch circuit 6. As a result, the error flag F is set inside the latch circuit 6.
is set to "1". Furthermore, the ECC decoder 1b reversely converts data B into data A.

When the data A thus obtained is output to the data bus 4 via the data output 65, the error 7 lag F is also output to the data bus 4 via the flag signal line 7 in synchronization with this.
is output to. Then, since the error flag F input from the data bus 4 is "1", the CPU can detect that there is a defective cell at the address where data A (actually data C) was stored. can.

Furthermore, if no error is detected by the ECC decoder 1b, the error signal E remains inactive.
The error 7 lag F is output to the data bus 4 as it is "0". Thereby, the CPU can also know that there is no defective cell at the address from which the data was read.

Note that the error signal E and error flag F are stored in the EEPROM.
Each time the read address of the memory section 2 changes, it is reset once, and the above-described process is repeated when a data read operation of a new address is started.

In this way, the CPU can recognize the existence of a defective cell, and therefore writes data only to normal memory cells without writing to the address where it is determined that a defective cell exists (for example, It becomes possible to write data to another address without using the address where the cell exists.

Also, if writing to a defective cell is avoided, the EEPRO
Even if the number of defective cells increases in the M memory section 2, the ECC data]-
The number of error bits of the data C input to the data card 1b does not increase. Therefore, even if a defective memory cell occurs during data writing, the number of error bits in data C is limited, and in this case, correction is possible with the ECC decoder 1b and the data is not destroyed. Never.

In the above embodiment, the error signal E from the error signal generation circuit 3 is once latched by the latch circuit 6 and set as the error flag F, but at the same time when the data A is output from the ECC decoder 1b, the error signal E is directly The error signal generation circuit 3 may be configured to output the signal to the CPU. In this case, the latch circuit 6 is unnecessary.

Also, by adding an error address signal to the error signal E,
The address where the error occurred and the contents of the error signal E are temporarily stored in a predetermined memory (not shown), etc.
These pieces of information may be transmitted to the CPU after the data output operation has progressed to a certain extent. The error address signal at this time can be generated based on the error detection operation of the ECC decoder 1b. In this case, since the relationship between the address accessed for reading and the occurrence of an error at that address is stored as information, by synchronizing the output of data A from the ECC decoder 1b and the output of the error signal E, There is no need for the CPU to determine the relationship between the address and the occurrence of an error based on the output timing. of course,
The memory is not limited to EEPROM, and the number of data bits is not particularly limited. The error signal generation circuit may not be incorporated inside the error correction circuit, but may be provided outside the error correction circuit. The present invention is also applicable when the error correction circuit corrects errors not in units of 1 bit but in units of N bits (N≧2). The error correction principle is not particularly limited either, and any error correction code such as a Hamming code or a parity check code can be used.

〔Effect of the invention〕

As described above, according to the present invention, since a CPU can detect a defective storage cell in a memory, it is possible to avoid using a defective cell, and a microcomputer that can prevent data destruction can be obtained. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a storage section of a microcomputer according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a storage section of a conventional microcomputer. In the figure, 1 is an error correction circuit, 1a is an FCC encoder, 1b is an EEC decoder, 2 is an EEPROM memory section, 3 is an error signal generation circuit, E is an error signal, and F is an error flag. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a microcomputer equipped with an error correction circuit that detects and corrects errors in data stored in a readable/writable memory, a predetermined error signal is generated when the error is detected by the error correction circuit. 1. A microcomputer, comprising: an error signal generation circuit for generating an error signal; and an error signal generation notifying means for notifying a CPU of the microcomputer of the status of generation of the error signal.