JP2806856B2 - Diagnostic device for error detection and correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic device for an error detection and correction circuit, and more particularly to an error detection and correction code generation unit (hereinafter, referred to as an error detection and correction code generation unit)
It is called ECG department. ) And an error detection and correction unit (hereinafter referred to as EC
Part C. ).

[0002]

2. Description of the Related Art In order to improve the reliability of an information processing system, it is necessary to ensure normal operation of each component device. The error detection and correction circuit is mainly employed in a storage device, and can detect and correct a 1-bit error that may occur at the time of writing / reading. However, there is no malfunction of the error detection and correction circuit itself, and it is important to diagnose its normality.

Conventionally, various measures have been taken to diagnose such an error detection and correction circuit. For example, according to Japanese Patent Application Laid-Open No. 58-207155, test data is supplied to an ECG unit by a host device or a diagnostic control device.
Under the control of the diagnosis control unit, the polarity of a part of the output data of the control unit is inverted and input to the ECC unit. And ECC
By referring to the error detection signal sent by the
The normality of the ECG and ECC sections was diagnosed.

[0004]

In the above-described method of diagnosing the error detection and correction circuit, in order to improve the accuracy of the diagnosis, it is necessary to prepare a large number of test data patterns for the ECG unit and It is necessary to increase the pattern for inverting the polarity of a part of the output data signal. Therefore, it takes a long time to perform a reliable diagnosis with high reliability, during which time the host device and the diagnostic control device must be restrained.

That is, the host device or the diagnostic control device must include means for generating a large number of the above test data patterns, and a plurality of control signals for inverting the polarity of the output signal of the ECG unit must be set for each pattern. No.

SUMMARY OF THE INVENTION It is an object of the present invention to sequentially generate all patterns of test data without the intervention of a host device or a diagnostic control device, and to sequentially generate all polarity inversion patterns for each pattern. It is an object of the present invention to provide a diagnostic device for an error detection / correction circuit in which the above disadvantages are improved.

[0007]

According to the present invention, there is provided an error detection / correction circuit diagnostic apparatus according to the present invention, wherein an error detection / correction code is added to write data and written to a storage unit. An error detection / correction unit that detects and corrects a 1-bit error included in the data and sends it out as read data, wherein the error detection / correction code is added to the test data set by the counter via the error detection / correction code generation unit. The diagnostic data is generated by adding the diagnostic data, the diagnostic data is inverted bit by bit and input to the error detection and correction unit, and its normality is determined based on an error detection signal sent from the error detection and correction unit. Be composed.

Further, an error detection / correction circuit diagnostic apparatus according to the present invention includes an error detection / correction code generation unit for adding an error detection / correction code to write data and writing the same to a storage unit, and the data read from the storage unit. In a storage device having an error detection and correction unit for detecting and correcting a 1-bit error and transmitting the same as read data, test data for diagnosing an error detection and correction circuit including the error detection and correction code generation unit and the error detection and correction unit is stored. A flip-flop, a counter for sequentially changing and setting the test data, an adder for sequentially changing the content of the flip-flop and the content of the counter, and the test data via the error detection and correction code generation unit. A decode signal corresponding to a bit string of diagnostic data to which an error detection and correction code is added And a signal inverting circuit for receiving the diagnostic data and the decode signal, inverting any one bit of the diagnostic data, and sending the inverted signal to the error detection and correction unit. The unit is configured to detect whether or not to detect and correct the one-bit error generated by the signal inversion circuit.

Further, the diagnostic device for an error detection / correction circuit according to the present invention compares the data transmitted by the error detection / correction unit with the test data held in the flip-flop, and transmits an error signal when the two do not match. The comparator is configured to include a comparator.

That is, in the present invention, the test data to the ECG section is continuously changed by the adder. Therefore, all data patterns can be input to the ECG unit at high speed without using a host device.

Further, an input signal of a decoder used for inverting an output signal from the ECG unit is generated by an adder. Therefore, all error patterns can be generated at high speed without using a host device.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, a diagnostic device for an error detection and correction circuit according to the present invention includes an ECG unit 21 that adds an error detection and correction code to write data 31 and writes the same to a RAM unit 20; E is detected and corrected and transmitted as read data 32 E
In the storage device having the CC unit 22, a flip-flop (hereinafter, referred to as “test data”) holding test data 35 for diagnosing the error detection and correction circuit including the ECG unit and the ECC unit.
It is called F / F. ) 4, a counter 3 for sequentially changing and setting the test data, adders 1 and 2 for sequentially changing the contents of the F / F and the counter, and the test data 35 via the ECG unit. A decoder 5 for generating a decode signal corresponding to the bit string of the diagnostic data 36 to which the error detection and correction code is added according to the output signal of the counter; And a signal inverting circuit 6 for inverting the signal and sending the inverted signal to the ECC unit.

Further, the selectors 23 and 24 have a function of switching between a normal operation mode and a diagnostic mode, and are activated by a diagnostic mode select signal 33.

The F / F 4 has a 4-bit configuration using the output of the selector 23 as an input signal and has a reset function. The counter 3 is a 3-bit F / F using the output of the adder 2 as an input signal, and has a reset function. Further, the adder 2 takes the output of the counter 3 as an input signal, adds "1" to the input signal, outputs the result, and inputs it to the counter 3 again. At this time, if an overflow occurs, it is sent to the adder 1 as an overflow signal 34. Then, at this time, the adder 1 adds "1" to the output signal of the F / F4 and outputs it, and inputs this to the F / F4 to make new test data 35.

Next, the operation of the diagnostic device for the error detection and correction circuit will be described.

First, during normal operation, in a data write operation to the RAM section 20, the diagnostic mode select signal 33 is at logic "0". At this time, the write data 3 is stored in the F / F 4.
1 is input. And the output signal of F / F4 and EC
The output signal of the G unit 21 is input to the RAM unit 20.

In a data read operation from the RAM section 20, an output signal of the RAM section is input to the ECC section 22, and an output signal of the ECC section in which an error in the input data is detected and corrected becomes read data 32.

At the time of diagnosis, the diagnostic mode select signal 33 becomes logic "1". The reset signal causes the F / F
4 and the initial value of the counter 3 are set to "0". At this time, the output of the decoder 5 becomes “10000000”, and the signal inverting circuit 6 inverts bit 0 of the diagnostic data 36,
Input to C section 22.

At this time, the ECG unit 21 and the ECC unit 22
Is normal, the ECC error detection signal 37 becomes logic "1".
Becomes The ECC error detection signal 37 is always observed, and if it is other than the logic "1", it is understood that the ECC error is abnormal.

Next, the value of "001" is input to the counter 3 by the adder 2. At this time, F / F4 is “000”
0 ”, but the output of the decoder 5 is“ 01000 ”.
000 ", and the signal inverting circuit 6 inverts the bit 1 of the diagnostic data and inputs it to the ECC unit 22. At this time, by observing the ECC error detection signal 37, the abnormality of the circuit can be known.

In the same manner, diagnosis is performed until the counter 3 becomes "111". Thereafter, when the counter 3 becomes “000”, the overflow signal 34 of the adder 2 becomes “1”. At this time, the adder 1 adds “1” to the input signal to “00”.
01 is input to the F / F 4. Thereafter, diagnosis is performed until the value of the counter 3 changes from "000" to "111".

That is, as described above, the F / F4 is changed from "0000" to "1111", and the diagnosis is performed in a pattern in which the diagnostic data 36 is inverted one bit at a time in each case.

FIG. 2 is a block diagram showing another embodiment of the present invention. In the figure, the diagnostic device of the error detection and correction circuit of the present invention includes a comparator 7 for comparing output data of the ECC unit 22 with test data 35 held by the F / F 4 in a diagnostic mode. The comparator 7 sends out a comparison error detection signal 38 when the two do not match. Configurations and functions other than those described above are the same as those shown in FIG.

In FIG. 2, in the diagnostic mode, the comparator 7
Compares the output data of the ECC unit 22 with the test data 35, and if they match, sets the comparison error detection signal 38 to logic "0". Therefore, the ECC error detection signal 37 and the comparison error detection signal 38 are always observed, and the ECC error detection signal 37 becomes the logic “1” and the comparison error detection signal 3
If 8 is other than logic "0", it is understood that an abnormality has occurred.

That is, in addition to the presence / absence of the ECC error detection signal, the normality of the error is diagnosed with high accuracy by observing the comparison error detection signal obtained by comparing the input data to the error detection / correction circuit with the output data. be able to.

[0027]

As described above in detail, according to the present invention, by providing an adder and a signal inverting circuit for generating test data, diagnosis of the ECG section and the ECC section can be performed with all data patterns. Can be. That is, there is an effect that the normality of the error detection and correction circuit can be accurately diagnosed in a short time without the intervention of a host device or a diagnostic control device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

 1, 2 adder 3 counter 4 F / F 5 decoder 6 signal inverting circuit 7 comparator 20 RAM unit 21 ECG unit 22 ECC unit 23, 24 selector 33 diagnostic mode select signal 37 ECC error detection signal 38 comparison error detection signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 11/08 320 G06F 11/22 G06F 12/16

Claims (2)

(57) [Claims] 1. An error detection and correction code generation unit for adding an error detection and correction code to write data and writing the data to a storage unit, detecting and correcting a 1-bit error included in data read from the storage unit, and transmitting the data as read data. And a flip-flop for holding test data for diagnosing an error detection and correction circuit including the error detection and correction code generation unit and the error detection and correction unit, and sequentially changing the test data. A counter to be set, an adder for sequentially changing the contents of the flip-flop and the contents of the counter, and a bit string of diagnostic data obtained by adding an error detection and correction code to the test data via the error detection and correction code generation unit. A decoder for generating a corresponding decode signal according to the output signal of the counter; And a signal inverting circuit for receiving the decode signal, inverting any one bit of the diagnostic data, and sending the inverted signal to the error detection and correction unit, wherein the error detection and correction unit generates A diagnostic device for an error detection and correction circuit, which detects whether or not a bit error is detected and corrected. 2. A diagnostic device for an error detection and correction circuit according to claim 1 , wherein data transmitted by said error detection and correction unit is compared with test data held in said flip-flop, and an error signal is output when both data do not match. A diagnostic circuit for an error detection and correction circuit, comprising: