JPH11219323A - Data path fault detection method and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data path fault detection method and an information processor, by which software in the processor writes/reads data in a register in an objective controller into/from a register at prescribed intervals and the fault of a data path can always be detected without the need of parity functions for the processor and the objective controller. SOLUTION: In the data path fault detection method for detecting the fault of the data path contains a stage for writing same data in first and second registers 4 and 11 provided at both ends of the data path and a stage for comparing data stored in the first and second registers 4 and 11. Furthermore, a data path fault detection program and the information processor operating based on the method are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to detection of a hardware failure in an information processing apparatus, and more particularly, to a failure of a data path between a processor and a device controlled by the processor (hereinafter referred to as a controlled device). Regarding detection.

[0002]

2. Description of the Related Art Conventional fault detection in a data path between a processor and a device to be controlled includes fault detection by parity check and fault detection by initial diagnosis.

In the failure detection by the parity check, a data path failure is detected by performing a parity check between the processor and the device to be controlled. Therefore, a parity generation circuit, a parity comparison circuit, and a path for a parity signal are required.

FIG. 3 shows an example of an information processing apparatus for diagnosing a data path failure by parity check. The connection between the processor 6 and the control target device 7 requires a data signal line 25 and a parity signal line 26. This is because a 1-bit parity signal is required for one byte (8 bits) of the data signal. For example, when the data is 4 bytes, four parity signals are required, and when the data is 8 bytes, eight parity signals are required separately from the data signal.

On the other hand, in the failure detection by the initial diagnosis, a test program is executed at the time of the initial diagnosis operation of the information processing apparatus to perform a data write / read operation.
Performs data path failure detection.

[0006]

In the failure detection by the parity check, there is a disadvantage that the number of input / output pins of both the integrated circuit including the processor and the control target device is increased by the amount required for the parity signal. In addition, realization of the parity function requires a parity generation circuit and a parity comparison circuit, which has the disadvantage that the circuit becomes complicated.

On the other hand, the failure detection by the initial diagnosis is performed at the time of the initial diagnosis of the apparatus. However, there is a disadvantage that the failure detection cannot be performed after the information processing apparatus shifts to the normal operation.

The problem to be solved by the present invention is that neither the processor nor the target control device requires a parity function,
It is an object of the present invention to provide a data path failure detection method and an information processing device which can always detect a data path failure by writing and reading data in a register in a target control device by software in a processor at regular intervals.

[0009]

In order to solve the above-mentioned problems, the present invention relates to a data path failure detecting method for detecting a failure in a data path, wherein first and second registers provided at both ends of the data path are provided. And a step of comparing the data stored in the first and second registers with each other.

The data path failure detection method of the present invention will be described more specifically. In a data path failure detection method for detecting a failure of a data path connecting a processor of an information processing device and a control target device, Writing data to a first register provided on the control target device side of the data path, and writing the same data to a second register provided on the processor side of the data path; Reading the first data stored in the register via the data path and reading the second data stored in the second register; and the step of the processor comparing the first and second data. A data path failure detection method characterized by including:

The data path failure detection method of the present invention can be executed as a data path failure detection program. Therefore, the present invention provides a storage medium storing a data path failure detection program for detecting a failure of a data path connecting a processor of an information processing device and a control target device, wherein the data is stored in a first register provided in the control target device. While writing the same data to a second register provided on the processor side, and the processor reads out the first data stored in the first register via a data path, A data readout process for reading out the second data stored in the second register and a data comparison process in which the processor compares the first and second data with the information processing apparatus. Provided is a machine-readable recording medium on which a detection program is recorded. In this case, the data path failure detection program can constantly monitor a data path failure by repeating data write processing, data read processing, and data comparison processing at predetermined time intervals.

An information processing apparatus for executing a data path failure operation detecting method according to the present invention is an information processing apparatus having a data path therein, the information processing apparatus having a first register at one end of the data path and a second register at the other end of the data path. A second register and a comparison circuit for comparing data stored in the two registers, wherein after writing the same data in the first and second registers, the comparison circuit reads data from the first and second registers; Are read and compared. Further, in an information processing apparatus including a processor, a control target device, and a data path connecting the processor and the control target device, the processor includes a first register and a comparison circuit, and the control target device includes a second register. And after writing the same data to the second register and the second register, the comparison circuit reads the data from the first and second registers and compares them.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus according to the present invention includes a plurality of general-purpose registers capable of writing / reading command data, and a comparison circuit for comparing outputs of the general-purpose registers. And a failure detection of a data path between the control target device having a writable / readable register.

A configuration of an information processing apparatus 1 according to an embodiment of the present invention will be described with reference to FIG.

The information processing device 1 includes a processor 2 and a control target device 3. The processor 2 writes data /
It has a readable general-purpose register 4 and a comparison circuit 5, and has no parity function. The control target device 3 is controlled by the processor 2, has a writable / readable register 11, and does not have a parity function like the processor 2. The processor 2 and the control target device 3 are connected by a data path 21.

Next, the operation of the information processing apparatus 1 will be described with reference to FIG.

At the time of normal operation of the information processing apparatus 1, the processor 2 writes / reads instructions / data / reads data to / from the control target apparatus 3.

At a predetermined time interval (for example, every one second), the information processing apparatus 1 shifts from the normal operation to the failure detection operation (104).

At the time of the failure detection operation, the processor 2 first
At the same time that a write command is issued to the register 11 to write data to the register 11 via the data path 21, a write command is also issued to the register 4 to write data (1
01).

Next, the processor 2 reads out the data stored in the register 11 via the data path 21 and sends it to the comparison circuit 5, and at the same time compares the data stored in the register 4 via the data path 22. The data is transmitted to the circuit 5 (102).

The comparison circuit 5 receiving the data from the registers 4 and 11 compares the two data (103). As a result of the comparison, if the data stored in the registers 4 and 11 match, the processor 2 returns to the normal operation, and executes the failure detecting operation again after a specified time. If the two data do not match, an error is notified to the outside of the device.

By repeating this, it is possible to always detect the failure of the data path between the processor 2 and the device 3 to be controlled.

[0023]

According to the data path failure detection method and information processing apparatus of the present invention, data path failure detection can be performed at all times without requiring a parity function. The configuration of the information processing apparatus can be simplified without any loss.

As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to these embodiments, and it is understood that changes and improvements can be made within the ordinary knowledge of those skilled in the art. Of course.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus 1 according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of the information processing apparatus 1.

FIG. 3 is a block diagram of a conventional information processing apparatus 10 that detects a failure by a parity check.

[Explanation of symbols]

 1, 10 Information processing device 2, 6 Processor 3, 7 Control target device 4, 11, 15 Register 5 Comparison circuit 16 Parity generation circuit 17 Parity comparison circuit 21, 22 Data path 25 Data signal line 26 Parity signal line

Claims (6)

[Claims] 1. A data path failure detection method for detecting a failure in a data path, comprising: writing the same data to first and second registers provided at both ends of the data path; Comparing the data stored in the registers of the data path. 2. A data path failure detection method for detecting a failure of a data path connecting a processor of an information processing device and a control target device, the method being provided on the control target device side of the data path via the data path. Writing the same data to a second register provided on the processor side of the data path, and writing the same data to a second register provided on the processor side of the data path. While reading out the data via the data path,
A method of detecting a data path failure, comprising: reading out second data stored in the second register; and comparing the first and second data by the processor. 3. A recording medium storing a data path failure detection program for detecting a failure in a data path connecting a processor of an information processing device and a control target device, wherein the data is stored in a first register provided in the control target device. And the second provided on the processor side.
A data write process of writing the same data to the register of the processor; and the processor reads out the first data stored in the first register via the data path,
A data read process for reading second data stored in the second register, and the processor causes the information processing device to execute a data comparison process for comparing the first and second data. A machine-readable recording medium that records a data path failure detection program. 4. The recording medium according to claim 3, wherein said data path failure detection program repeats said data write processing, data read processing and data comparison processing at predetermined time intervals. A readable recording medium. 5. An information processing apparatus having a data path therein, comprising: a first register at one end of the data path, and data stored in a second register and two registers at the other end of the data path. A comparison circuit that writes the same data to the first and second registers, and then reads the data from the first and second registers and compares the data. Processing equipment. 6. An information processing apparatus comprising a processor, a control target device, and a data path connecting the processor and the control target device, wherein the processor includes a first register and a comparison circuit, and the control target device includes a second register. An information processing apparatus comprising: a register; and after writing the same data to the first and second registers, the comparison circuit reads data from the first and second registers and compares the data.