JPH01309421A - Error correction system - Google Patents

Abstract

PURPOSE:To prevent mis-detection of a memory error by correcting a data if an error takes place in the data, storing the result in a data storage means and applying error detection again. CONSTITUTION:A microprogram and a corresponding ECC are stored in a control storage(CS) 211 and the data read from the CS 211 are stored in a read data latch 223. An error detection section 231 detects the data error and in the presence of 1-bit error in the readout data, an error correction section 241 corrects the data and writes it in the CS 211 and stored in the read data latch 223, an error is detected from the stored correction data and if any error takes place again, it is discriminated that the CS 211 is faulty and when no error exists, it is discriminated that logical elements other than the CS 211 have a fault.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Working Examples ■, Correspondence between the Examples and FIG. 1 ■ , Structure of the embodiment ■, Operation of the embodiment (i) During normal operation (ii) When a 2-bit error occurs (iii) When a 1-bit error occurs for the first time (iv) When re-executing ■, Summary of the embodiment ■ 3 Inventions [Summary] The purpose of this invention is to prevent erroneous detection of memory errors with respect to an error correction method that reads data including an error correction code and determines the location of an error when an error occurs. a memory for storing data including an error correction code; a data holding means for storing data read from the memory; an error detecting means for detecting errors based on the data stored in the data holding means; A correction means for correcting the data stored in the data holding means when an error is detected by the detection means and storing the corrected data in the data holding means, and determining the location of the error based on the detection result by the error detection means. When an error occurs, the correcting means corrects the data, and the location where the error occurs is determined based on the presence or absence of an error in the corrected data.

[Industrial application field]

The present invention relates to an error correction method, and more particularly to an error correction method that reads data including an error correction code and determines the location where an error occurs when an error occurs.

[Conventional technology]

In recent years, with the development of semiconductor technology, the degree of integration of logic elements used in computers has improved and the calculation cycle time has been shortened. Additionally, as the functionality of logic elements improves,
This causes problems such as a deterioration in the retention of elements and an increase in the defective rate of elements.

To deal with such problems, there is a method of adding an error correction code (hereinafter referred to as ECC) to data.

For example, an error correction code (hereinafter referred to as ECC) is added to data stored in a memory or the like, and errors are verified when the data is read out, and data is corrected when an error occurs.

FIG. 4 shows the configuration of a conventional example for correcting read data.

In this case, a correction circuit for correcting data read from the memory 411 includes a write data launch 463 that temporarily holds data to be supplied to the memory 411, and a correction circuit for correcting data read from the memory 411.
11 and an address latch 453 that temporarily holds address data supplied to the memory 411. An error detection unit 431 that performs error detection by comparing the error address latch 455 and the ECC portion of data with other portions.
, an error correction control section 441 that performs control according to the detection result of the error detection section 431, an error correction section 443 that performs data correction, and two selectors 45'l and 461.
It is equipped with

When storing data in the memory 411, first, data including ECC is stored in the write day clutch 463 via the selector 461. Further, address data is stored in the address latch 453 via the selector 451.

Next, the address data stored in the address latch 453 and the data stored in the write day clutch 463 are supplied to the memory 411, and the memory 411 stores the write data clutch 463 in the storage location specified by the address data.
Stores data supplied from.

FIG. 5 shows the operating procedure when error correction is performed on read data.

First, data is read and stored in the read day clutch 421 (step 511). In the same manner as the data storage operation to the memory 411, address data is supplied from the address latch 453 to the memory 411, and the corresponding data is read and stored in the read data latch 421.

Next, the error detection unit 431 detects the read data latch 42
Error detection is performed by comparing the read data (data other than ECC) stored in 1 and the ECC, and the detection result is sent to the error correction control unit 441 (step 512).

The error correction control unit 441 determines whether or not there is an error in the read data according to the detection result (step 5).
13). If a negative determination is made (if there is no error), the process returns to step 511 and repeats the process.

If an affirmative determination is made in step 513 (if there is an error), the error correction control section 441 sends an error signal to the error correction section 443. Upon receiving the error signal, the error correction unit 443 corrects the read data according to the read data and ECC stored in the read data clutch 421 (step 514).

Next, the data (read data and ECC) corrected by the error correction unit 443 is written into the memory 411 (step 515). The address data corresponding to the data in which the error has occurred is held in the error address latch 455, and is sent to the address launch 453 via the selector 451.
Store the address data in . Further, the corrected data output from the error correction unit 443 is sent to the selector 46.
1 to the light day clutch 463.

Thereafter, the write data latch 463 is stored in the storage location specified by the address data stored in the address launch 453.
The corrected data stored in is stored.

(Problem to be solved by the invention) By the way, in the above-mentioned conventional method, the memory 411
If an error occurs due to a failure in a logic element other than the above (read day clutch 421, error detection unit 431, etc.), a memory error (hardware failure in the memory 411 or software failure in stored data) is erroneously detected. There was a problem with this.

For example, even if the data read from the memory 411 is normal, when the error detection unit 431 erroneously detects an error, the error correction unit 443 corrects the data,
The corrected data (erroneous data) is stored again in the memory 411. In particular, recently, as the degree of integration of logic elements has increased, the frequency of failures occurring in logic elements other than the memory 411 has also increased, so it is necessary to correct data errors and deal with failures in elements other than the memory 411. There was a desire for an error correction method that could do this.

The present invention was created in consideration of these points, and an object of the present invention is to provide an error correction method that can prevent erroneous detection of memory errors.

[Means to solve the problem]

FIG. 1 is a principle block diagram of the error correction method of the present invention.

In the figure, memory 11 stores data including error correction codes.

The data holding means 121 stores data read from the memory 11.

The error detection means 131 performs error detection based on the data stored in the data holding means 121.

When the error detection means 131 detects an error, the correction means 141 corrects the data stored in the data holding means 121 and stores the corrected data in the data holding means 121.

The determining means 151 determines the location where the error has occurred based on the detection result by the error detecting means 131.

Therefore, as a whole, when an error occurs in data, the correction means 141 corrects the data and stores it in the data holding means 121, and the error detection means 131 performs error detection again.

[For production]

The memory 111 stores data including error correction codes. The data is read from the memory 111 and stored in the data holding means 121, and the error detection means 131 performs error detection based on the data.

When the error detection means 131 detects an error, the correction means 1
41 corrects the data stored in the data holding means 121 and holds it in the data holding means 121 again. The error detection means 131 performs error detection again based on the corrected data stored in the data holding means 121.

The determining means 151 determines the location where the error has occurred in accordance with the detection result by the error detecting means 131.

In the present invention, when an error occurs in data, the correction means 141 corrects the data, stores it in the data holding means 121, and detects the error again. Based on the result, the location where the error occurs can be determined. Therefore, erroneous detection of memory errors can be prevented.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment to which the error correction method of the present invention is applied.

Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The memory 111 includes a control memory (hereinafter referred to as C3) 211
corresponds to

The data holding means 121 corresponds to the retard clutch 223.

The error detection means 131 corresponds to the error detection section 231° and error correction system'41-251.

The correction means 141 corresponds to the error correction section 241.

The determining means 151 corresponds to the error correction control section 251 and the re-execution flag 253.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

In FIG. 2, a system (for example, a computer system) to which the error correction method of the present invention is applied has a C3211 that stores a microprogram and a corresponding ECC, and a readout microprogram and ECC. an error detection section 231 that detects errors by comparing with the error detection section; an error correction control section 251 that performs control associated with error detection; an error correction section 241 that corrects data (microprogram) when an error occurs; A re-execution flag 253 that stores flags depending on the presence or absence, a write day clutch 263 that holds the microprogram and ECC stored in the C3211, and a write day clutch 22 that holds the microprogram and ECC read from the C3211.
3, an address latch 273 that holds address data to be supplied to the C3211, an error address latch 275 that holds address data when an error occurs, and three selectors 221 and 261 that select and output one of the two.
．． We are equipped with 271.

Address data for performing the address terminal of C3211 is introduced into the first input terminal of the selector 271. The output terminal of the selector 271 is connected to the input terminal of the address latch 273, and the output terminal of the address latch 273 is connected to the C
3211 address terminal and error address latch 27
It is connected to the input terminal of 5. Error address latch 2
The output terminal of 75 is connected to the second input terminal of selector 271.

Further, write data (microprogram and corresponding ECC) to be stored in the C3211 is introduced into the first input terminal of the selector 261. The output end of the selector 261 is connected to the input end of the light day clutch 263, and the output end of the light day clutch 263 is connected to the data terminal (input side) of the C3211.

The data (microprogram, ECC) output from the data terminal (output side) of the C3211 is sent to the selector 221.
is supplied to the first input terminal of. The output end of the selector 221 is connected to the input end of the read-date clutch 223, and the output end of the saw 1-data latch 223 is connected to the input end of the error detection section 231 and the error correction section 241.

The error detection unit 231 performs error detection based on data supplied from the retard clutch 223. The detection result is supplied to the error correction control section 251.

The error correction control unit 251 is connected to the re-execution flag 253 and the error correction unit 241, and is connected to the error detection unit 23.
] In accordance with the detection result from the error correction unit 241, the re-execution flag 253 is set or reset, and an instruction is sent to the error correction unit 241.

It is assumed that each latch and each selector operate in response to an instruction signal sent from the error correction control section 251, and the connection line with the error correction control section 251 is omitted in the figure.

Write data to C3211 (micro program, EC
When writing in C), first write data latch 2
63 holds the write data introduced via the selector 261, and these are supplied to the data terminal (input side) of C3211.

Further, the address latch 273 holds address data introduced via the selector 271, and the address data is supplied to the address terminal of the C3211.

The C3211 stores the write data supplied to the data terminal in the storage location specified by the address data supplied to the address terminal.

When reading the microprogram stored in the C3211, the address launch 273 first holds the address data introduced via the selector 271, and the address data is supplied to the address terminal of the C3211.

C3211 executes the microprogram and E stored in the location specified by the supplied address data.
Output CC. These data are held in read data latch 223 via selector 221. The microprogram held in the read day clutch 223 is
The data is loaded into a processing device (not shown) and executed.

Plate - Two Rakutō II additions Next, the operation of the embodiment of the present invention described above will be explained.

Currently, as an ECC that supports microprograms,
Let us consider a code for 1-bit error correction and 2-bit error detection, and assume that the error detected in the embodiment is either a 1-bit error or a 2-bit error.

FIG. 3 shows the operating procedure in the embodiment.

''±1 Normalization First, the microprogram and FCC are read from the C3211 (step 311). These read data are held in the beam-dove-clutch 223.

Next, the error detection unit 231 performs error detection on the read data (step 312). As a detection result,
Information such as whether an error has been detected and whether it is a 1-bit error or a 2-bit error is sent to the error correction control section 251.

Next, the error correction control unit 251 determines whether or not it is a re-execution process (step 313).

During the first error detection process for data read from the C3211 (when the re-execution flag 253 is in a reset state), a negative determination is made and it is determined whether an error has occurred (step 314). If no error is detected, a negative determination is made.

Thereafter, the process returns to step 311 and repeats the process.

The error correction control unit 251 sends an instruction to the address latch 273 to read the next microprogram.

(ii 2-hit error raw ■ Affirmative judgment in step 314 (if an error occurs)
Then, the error correction control unit 251 determines whether the error that has occurred is a 2-pits-1 error (step 315). If a 2-bit error occurs, an affirmative determination is made.

Next, the error correction control unit 251 stops the microprogram reading process (step 316), notifies the user of the occurrence of a failure (step 317), and ends the process. For example, it sends an error signal to the external processing device 8 to indicate the occurrence of a 2-bit error, or lights up a 2-bit error warning lamp.

1i110 1 hit error raw■, step 315
If the determination is negative (if it is not a 2-bit error, that is, if it is a 1-bit error), then the error correction control unit 251 sets the re-execution flag 253 (data "1").
"" is stored) (step 318).

The error correction control unit 251 also controls the error correction unit 241.
The error correction unit 241 corrects the microprogram according to the instruction (step 31).
9). The error correction unit 241
The microprogram and ECC held in 3 are read out, and error pits in the microprogram are corrected.

Next, the corrected microprogram and the corresponding ECC are stored in the C3211 (step 320). By switching the selector 271, the error address latch 27
The address data at the time of error occurrence, which is held in 5, is held in the address latch 273. The address data held in the address latch 273 is supplied to the address terminal of the C3211. Also, the selector 261 is switched to hold the corrected microprogram and ECC in the write data latch 263. Those data held in the write 1-data latch 263 are supplied to the data terminal of the C3211.

Further, the selector 221 is switched to hold the corrected microprogram and ECC in the read day clutch 223 (step 321).

Thereafter, the process returns to step 312 (error detection) and repeats the process.

” If the determination in step 313 is affirmative (if the re-execution flag 253 is set in step 318),
Next, the error correction control unit 251 stops the microprogram reading process (step 322) and determines whether an error has occurred (step 323).
.

If an affirmative determination is made, the error correction control unit 251 performs C8211
An error signal indicating that a failure has occurred is output (step 324), and the process ends.

Further, if a negative determination is made in step 324, the selector 221 other than C8211. Lead day clutch 223. Error detection unit 231. An error signal indicating that a failure has occurred in any of the error correction units 241 is output (step 3).
25), the process ends.

(2) - Summary of I In this way, the microprogram and the corresponding ECC & are stored in the C3211, and the data read from the C3211 is stored in the read data latch 223. The error detection unit 231 detects an error in the data,
If there is no error in the data, data reading from C3211 is continued.

Also, 1 is added to the data read from C3211 (data supplied from C8211 to read day clutch 223).
When there is a hit error, the error correction section 241 corrects the data, writes the corrected data to the C3211, and holds it in the read data clutch 223.

Next, error detection is performed on the corrected data held in the read day clutch 223, and if another error occurs, it is determined that there is a failure in C3211, and if no error occurs again, C3211 It is determined that there is a fault in a logic element other than the above.

If the error detection unit 231 detects a 2-bit error, it is impossible to correct the data and it is also impossible to determine the location of the fault as described above, so the 2-bit error is notified to the outside and the process is terminated.

Therefore, when an error occurs in the data read from C3211, by correcting the data and performing error detection again on the corrected data, you can determine the fault location where the error occurred (C321) or (Whether it is a logic element or not) can prevent erroneous detection of memory errors.

]4 [Diagnosis ■] In addition, in the embodiment of the present invention described above, C8211
Although a control memory for storing microprograms has been considered, the present invention can also be applied to other memories (ROM, RAM, etc.).

When a read-only element such as a ROM is considered as the memory, the process of step 320 (memory rewriting) in FIG. 3 is omitted.

In addition, the ECC of the embodiment includes 1-bit error correction,
Although we have considered a method that detects 2-bit errors, any method that can correct the corresponding data may be used.

Furthermore, in "1. Correspondence between Examples and FIG. 1",
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, when an error occurs in data, the correction means corrects the data and stores the corrected data in the data holding means, and the location where the error occurs is determined based on the result of error detection again. Therefore, it is possible to prevent erroneous detection of memory errors, which is extremely useful in practice.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the error correction method of the present invention, Fig. 2
The figure is a block diagram of an embodiment to which the error correction method of the present invention is applied, Figure 3 is an explanatory diagram of the operation of the embodiment, Figure 4 is a diagram of the configuration of a conventional example, and Figure 5 is an explanatory diagram of the operation of the conventional example. be. In the figure, 111 is a memory, 121 is a data holding means, 131 is an error detection means, 141 is a correction means, 151 is a discrimination means, 211 is a C3, 221, 261, 271 are selectors, 223 is a read day clutch, 231 is an error 241 is an error correction unit, 251 is an error correction control unit, 253 is a re-execution flag, 263 is a write day clutch, 273 is an address latch, and 275 is an error address latch. I hit the book 0I (Fi Ri Fu Pa D Waku Shame 1st Figure ryo P soil purchase, I was talented) B's work 6 days Figure 5 Mu So Q composition diagram Figure 4

Claims (1)

[Claims] (1) Memory (1
11), a data holding means (121) for storing data read from the memory (111), and an error detecting means (131) for detecting errors based on the data stored in the data holding means (121). , correction means (141) for correcting the data stored in the data holding means (121) and storing the corrected data in the data holding means (121) when the error detecting means (131) detects an error; ), and determining means (151) for determining the location of the error occurrence based on the detection result by the error detecting means (131), and when an error occurs, the correcting means (14)
An error correction system characterized in that the data is corrected in step 1) and the location where the error occurs is determined based on the presence or absence of an error in the corrected data.