JPS60238933A - Error processing system of control storage device - Google Patents

Abstract

PURPOSE:To improve the processing speed of a control storage device, by correcting an ECC code error after a microinstruction is executed when the ECC code error having no direct relation with the execution of the microinstruction occurs. CONSTITUTION:At the time of readout, an address is latched by a register CSA and a control storage device CS is accessed by means of the latched address, and thus, data, parity bit, and ECC code are read out. When the results of inspections made by a parity checking circuit PC and ECC checking circuit ECC-C are normal, data from the control storage device CS are sent to an execution register CSE through a gate G3 and a microinstruction is executed. When no error is detected at the parity checking circuit PC, but 1-bit error is detected at the ECC checking circuit ECC-C, the data from the control storage device CS are latched by the execution register CSE and the microinstruction is exectuted, since no error occurs in the data and parity bit.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an error handling method for a control storage device of an electronic computer.

Prior Art and Problems A microprogram-controlled computer is equipped with a control storage (C3 for short), and the C8
In addition to microinstructions (data), the ECC code for error checking and correction of the data is stored. A parity bit is widely used for error checking, but if an ECC code is added, a parity bit is usually not provided. However, ECC check (error check and correction using ECC code) takes time compared to parity check. When the data is transferred, the data will be executed, but there is a risk that the clock that controls the data acquisition to the C8E will not be stopped in time). Become slow.

If the operation of the ECC circuit that checks and collects data during the read cycle of the control storage device C8 is not in time, when an error is detected, the cycle is immediately switched to the error correction cycle, and the microinstruction is executed after the error is corrected. There is a method, and in this error correction cycle O8
There is one that rewrites C8, and another that reports an error and rewrites C8 at the end of execution of a machine instruction.

However, in this method, an error correction cycle is entered even in the case of an error in the ECC code that is not directly related to the execution of the microinstruction, so the execution of the microinstruction is delayed by 1+ cycles.

Purpose of the Invention The present invention improves the above points, and executes the microinstruction if there is no error in the microinstruction itself, and rewrites C8 after the execution of the machine instruction (ECC: error correction in code, etc.). This is an attempt to speed up the execution of microprograms as much as possible.

Structure of the Invention The present invention provides an error handling method for a control storage device that stores microinstructions, in which a parity bit is stored in the control storage device together with the microinstruction and its ECC code, and a parity check circuit is provided in addition to the ECC check circuit. When a microinstruction is read from the control storage device, if the parity check circuit does not detect an error, the read microinstruction is executed, and if the ECC check circuit detects an error at this time, the error is canceled. If the parity check circuit detects an error when the microinstruction is processed and read out from the control storage device, the execution of the microinstruction is stopped and error processing is started. This will be explained with reference to.

EMBODIMENTS OF THE INVENTION The drawings illustrate embodiments of the invention. As shown in the figure, in the present invention, the control storage device CS stores a parity bit P in addition to data, that is, microinstructions and their ECC codes, and is provided with a parity bit generation circuit PG and a parity check circuit pc. C8W is a register for write data to the control storage device, ECC-G is an ECC code generation circuit, and ECC-C is an ECC check circuit. Further, C3A is a register of the address to access the control storage device C8, ADC is a counter of the address, and C3C is a register of the address to access the control storage device C8.
5 control circuit. Also, C'SD is the control storage device C8.
SYD is a syndrome bit register indicating an error position, 5ERC is a 1-bit error correction circuit, and C3E is a C5 execution register.

The data to be written to control memory C8 is launched into register C8W and then written to C3, where generation circuits PG and ECC-G generate parity bits and an ECC code, which are written to C8 along with the data. be included. Parity bits are added in byte units, and in this example C
Since the data of 8 is 4 bytes, the parity is 4 bits. ECC code can correct 1 bit error and
The code should be able to detect bit errors. For reading, the address is latched into register C3A, and the latched address accesses C8 to read the data, its parity bit, and ECC code. These are parity check circuit PC2FCC check circuit ECC-
Sent to C1 read data register C8D, pc and E
A parity check and an ECC check are performed in the CC-C, and if the results are normal, the CS data is sent to the execution register C3E through the gate G3, and the data, ie, the microinstruction, is executed. It is the control circuit C8C that switches the gate G3 to the input a side, outputs 11Qt during the CS read cycle, and sets the gate G3 as described above.

Further, the error output of the PC (°01 in this case) opens the AND gate G2 through the inverter G4 and the OR gate G1, and inputs the clock CLK to the execution register C3E.

C3E takes in CS data with this clock. The above is a normal case, but if there is an error in the data, parity bit, or ECC code, the following operation is performed.

When an error is detected in the parity check circuit PC, P
The error output of C passes through gate G4 and gate G1, closes gate G2, and clock CLK is output to execution register C3E.
Prohibit input to .

At this time, the ADC detects C3A due to the error output from the PC.
Stop counting up. As a result, the CS data is stored in the execution register C3E, and the data, ie, the microinstruction, is not executed.

At this time, if the ECC check circuit also detects a 1-bit error, this is a 1-bit error in the CS data.
The CS data is corrected in the next correction cycle. This is a 1-bit error correction circuit 5E using the CS data in register C3D and the syndrome bit in register C3D.
The error-corrected CS data carried out by the RC is taken into the execution register C3E through the gate G3 and executed.

At this time, C8C switches G3 to the input side and opens gate G2 through gate G1. On the contrary, EC
If no error is detected in the C circuit, this is a parity bit error, and the parity bit is corrected by creating a parity bit from the data in the next correction cycle. This correction does not need to be performed if parity check is not performed in the execution cycle, but the correction cycle exists because execution of the microinstruction is stopped. In either case, since C8 is not rewritten, an error is reported when the execution of the machine instruction ends, and C8 is rewritten. Furthermore, if the parity check circuit detects an error and the ECC check circuit detects a 2-bit error, error correction is impossible; in this case, the parity check circuit does not detect an error, and the ECC check circuit detects a 2-bit error. The same processing as when a bit error is detected is performed.

If the parity check circuit does not detect an error, but the ECC check circuit detects a 1-bit error, this is a 1-bit error in the ECC code, and there is no error in the data or parity bit.

Therefore, since there is no adverse effect even if the data (microinstruction) is executed, the clock is not stopped, and the CS data is latched to the execution register C3E to execute the data. However, when the machine instruction execution ends, an error report is made and the CS is rewritten (ECC code corrected). If the ECC check circuit detects a 2-bit error, it is impossible to correct the data, so after rewriting the C8, a micro-instruction retry or a machine instruction retry is performed.

As described in detail, in the present invention, a parity bit is added to the control storage device in addition to data, that is, microinstructions and ECC codes, and if there is a parity error, a correction cycle is entered, but if there is no parity error, the data is Since the instructions are executed, the instruction execution can be made as fast as possible, and high-speed data processing can be achieved.

[Brief explanation of the drawing]

The drawing is a block diagram showing an embodiment of the invention. In the figure, C8 is a control storage device, P is a parity bit, PC is a parity check circuit, and FCC-C is an ECC check circuit.

Claims (1)

[Claims] In an error handling method for a control storage device that stores microinstructions, a parity bit is stored in the control storage device together with the microinstruction and its ECC code, and a parity check circuit is provided in addition to the ECC check circuit. When the microinstruction in the control storage device is read, if the parity check circuit does not detect an error, the read microinstruction is executed, and if the ECC check circuit detects an error at this time, the error processing is executed. and further, if a parity check circuit detects an error when reading a microinstruction from the control storage device, the execution of the microinstruction is stopped and error processing is started. .