JPH02207355A - Memory readout system - Google Patents

Abstract

PURPOSE:To configure a system with high reliability by reading out program data written on a ROM in triplicate for one time of readout instruction for the ROM for three times, and comparing and collating them. CONSTITUTION:The same program is stored in #0, #1, and #2 areas of the ROM 6, and an address 2 from a CPU 1 are comprised of 16 bits of A0-A15. However, only the high-order bits A14 and A15 show counter values corresponding to the memory areas #0, #1, and #2 by the operation of a counter 5, and the counter values go to the address 11 of two high-order bits of the ROM. It follows that the ROM is read by changing a memory address for three times by modifying the address of the ROM by the counter values, and readout data 9 is inputted to the areas #0, #1, and #2 of a readout register 7, and the output are collated by a comparator 8, and majority logic decision is performed. In such a way, it is possible to improve the reliability for the readout data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory read method, and particularly to a measure for improving the reliability of read data in memory read.

[Conventional technology]

Conventionally, memory reading involves reading the contents of a memory according to a unique memory address. Further, in order to determine whether the information in the memory is correct or not, a 1-bit parity bit is added to a plurality of information bits to identify whether the information bits are odd or even numbers.

[Problem to be solved by the invention]

In the conventional memory read method described above, whether the read information is correct or not can be determined by parity pits, but
There are disadvantages in that errors in information cannot be detected unless a 2-bit error occurs, and even if errors are detected by parity pits, correct information cannot be obtained although it can be determined that the information is incorrect.

[Means to solve the problem]

The memory read method of the present invention includes a memory that stores the same information in a plurality of address areas, an address generation means that reads a plurality of pieces of information from the plurality of address areas of the memory in response to a single read instruction, and a memory that stores the same information in a plurality of address areas. It has a comparison circuit that compares a plurality of pieces of information to be read from the generated address, makes a majority decision, and extracts one piece of correct information.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart.

In FIG. 1, the CPUI outputs memory address 2. This memory address 2 is once latched by the address register 3. Of the 16 bits output from the address register 3, 14 bits are connected to the address line of the ROM (read only memory) 6 as the lower address 4.
The upper 2 bits are connected to the counter 5 and are connected to the address line of the ROM 6 as the upper address. In addition, R
OM6 is a 64-byte ROM, and during the manufacturing process the same program is stored in #O, #1, . It has already been stored in #2. Furthermore, the read data 9 of the ROM 6 is read from #0 of the read register 7.
#2, and each result becomes read data and is input to the comparison circuit 8.

Then, when the values of any two of the three read data are equal, the comparison circuit 8 transfers that value to the CPUI as CPU transfer data 10.

In Figure 2, address 2 is A 6 □ A 15 1
Consists of 6 bits, upper A 14. A 1g only in memory areas #O, #1 . #2
indicates the count value corresponding to the ROM.
The upper two bits of the address are 11. Modifying the ROM address with this count value means changing the memory address three times and reading the ROM, but it is invisible to the CPU, that is, the memory read operation from the CPUI is visible only once.

The read data 9 read out as described above enters #O, #1.12 of the read register 7, is compared by the comparator circuit 8, and a majority logic decision is made.

〔Effect of the invention〕

As explained above, in the present invention, in response to one read instruction from the CPU to the ROM, the program data written three times in the ROM is read out three times and compared and verified. Therefore, the normality of the program data and the resilience against partial bit corruption of the ROM can be guaranteed, and a highly reliable system can be constructed.

Furthermore, even if inexpensive, low-quality parts that are likely to cause memory bit corruption are used, reliability can be improved by increasing the plurality of majority logics.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart. 1... CPU (central processing unit), 3... address register, 5... counter, 6... ROM (read only memory), 7... read register, 8... comparison circuit.

Claims (1)

[Claims] a memory for storing the same information in a plurality of address areas; an address generating means for reading a plurality of pieces of information from the plurality of address areas of the memory in response to a single read instruction; and a plurality of pieces of information read from the address generated by the address generating means. A memory reading method characterized by comprising a comparison circuit that compares information, makes a majority decision, and extracts one piece of correct information.