JPH0136137B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a storage device, and particularly to an error correction method thereof.

(Prior Art) Conventional information processing devices use error correction codes such as Hamming codes, and in order to correct errors in one word of data read from random access memory such as RAM or ROM, error correction functions are required. A storage device is used which has the first
The configuration is as shown in the figure.

In FIG. 1, an example of a storage device includes an address register 1, a RAM or ROM 2, a selector 3, a data register 4, and an error correction circuit 5.

In FIG. 1, address register 1 and data register 4 each operate in synchronization with a clock signal, and one word of data whose address is the contents of first address register 1 is stored in RAM or
The data is read from the ROM 2 and set in the data register 4 through the cell vector 3.

The output of the data register 4 is transferred to other devices that require the data, but is also applied to the error correction circuit 5 at the same time.

If there is an error in the contents of data register 4,
After an error is detected and corrected, it is returned to the selector 3. Further, a signal line 105 is provided to inform other devices whether or not there is an error in the data on the output signal line 104.

Next, an example of the operation of the circuit shown in FIG. 1 will be explained in detail with reference to the timing chart shown in FIG.

The state of the signal on the output signal line 101 from address register ₁ changes at clock timing t1.
It shows address 200. One word of data from address 200 of RAM or ROM2 is sent to signal line 1.
04 as data 204, passes through the selector 3, and is set in the data register 4 at the next clock timing _t2 .

At clock timing _t2 , the error correction circuit 5 detects whether the data set in the data register 4 contains an error. If no error existed, the state of the signal on output signal line 105 would be a logic 0, and the device receiving the signal on output signal line 104 would have data 2.
04 is recognized as valid.

At this clock timing _t2 , the data on the output signal line 101 from the address register 1 indicates the address of address 201.

Data 205 stored at address 201 is set in data register 4 during clock timing _t3 in the same manner as described above. At this time, if an error is detected by the error correction circuit 5, the state of the signal on the output signal line 105 is a logical value of 1.
This causes other devices to know that the data 205 on the output signal line 104 is incorrect and invalid.

The error correction circuit 5 correctly corrects the data 205 as data 206, and connects the selector 3 to the signal line 106.
turn towards the side. Therefore, correct data 206 is set in the data register ₄ at clock timing t4. At clock timing _t4 , the data set in the data register 4 is correct, so the state of the signal on the output signal line 105 becomes a logical value 0.

Note that when moving from clock timing _t3 to clock timing _t4 , the contents of address register 1 are held so that they do not change. Thereafter, since the data set in the data register ₄ is correct at clock timings t4 and _t5 , the same operation as at clock timings _t1 and _t2 is performed. However, in this system, when errors are detected by the error correction circuit 5, even if there is an error in the ECC part of one word or less, it is treated and corrected in the same way as errors in other information bits. Therefore, if there is a fault in the ECC section in the word direction, the clock timing shown in Figure 2 will be changed when reading data.
A correction cycle such as t ₃ is inserted, and the clock timings t ₃ and t ₄ are repeated alternately, so the disadvantage is that only half of the time is there actually effective operation. It was hot.

(Object of the invention) The object of the invention is to
In a random access RAM or ROM having an ECC section, a parity check circuit is used to determine whether the bit in which the error occurred is in the data section or in the ECC section added for error correction. , a syndrome decoder,
The above-mentioned drawbacks are solved by providing a judgment logic circuit and a data section error correction circuit that corrects the error only when there is an error in the data section. An object of the present invention is to provide a storage device equipped with the configured error correction circuit.

(Structure of the Invention) A storage device according to the present invention includes at least a RAM/ROM, a register, and an error correction circuit,
The error correction circuit consists of a parity check circuit, a syndrome decoder, a judgment logic circuit, and a data section error correction circuit.

RAM/ROM is a random access type memory for storing information having an ECC part and a data part in one word.

A register is a circuit for holding information read from RAM/ROM.

The error correction circuit is a circuit for detecting and correcting an error when it exists in the contents held in the register.

The parity check circuit for configuring the error correction circuit is a circuit for performing a parity check on the data section and the ECC section. The syndrome decoder is a circuit that receives the output of the parity check circuit and outputs an indication signal of an erroneous bit based on a combination of parity error signals.

The decision logic circuit checks for the presence of an error based on the output of the syndrome decoder, and determines whether an error exists.
This circuit determines whether an error exists in the ECC section or the data section and instructs to correct only the error in the data section.

The data section error correction circuit is a circuit for correcting errors in the data section and returning them to the register.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 3 shows an embodiment of a storage device according to the present invention.

FIG. 3 shows an example of a control storage device for an information processing system, in which first to third registers 6,
9, 15 and the first to fifth selectors 7, 10, 1
3, 14, 18, register group 8, and adder 11
, RAM/ROM 12 , error correction circuit 16 ,
It is equipped with a flip-flop group 17.

The operation of the storage device will be explained below according to FIG.

In FIG. 3, microinstructions are stored in RAM/ROM 12.

The output of the second selector 10 determines whether the RAM/
All bits except the least significant bit (LSB) at the corresponding address in ROM 12 are accessed.
Whether the value of the least significant bit is 0 (the value appearing on the data signal line 116) or 1 (the value appearing on the data signal line 117) depends on the output of the fifth selector 18. It is configured to be selected by the third selector 13.

The selected one-word microinstruction is read out to the third register 15 via the fourth selector 14. This microinstruction is composed of first to fifth fields 19 to 23 as shown in FIG.

The first field 19 is a field for controlling the data path. For example, FIG. 6 is a diagram showing an example of a data path, which is comprised of fourth and fifth registers 24, 25, and an arithmetic logic unit (ALU) 26.

The first field 19 controls the write signals to the fourth and fifth registers 24 and 25 and the operation mode signal to the arithmetic logic unit 26 to perform the next operation.

That is, (4th register 24) + (5th register 2
5) → (4th register 24) (4th register 24) - (5th register 2
5)→(fifth register 25).

The second field 20 is a field for representing an instruction for controlling the operation sequence of the RAM/ROM 12.

The third field 21 is the second field 20
This is used to select the bit to be read when the TEST instruction is as shown in FIG.

The fourth field 22 is a field for setting branch destination addresses, calculation constants, and the like. The fourth field 23 is a redundancy field, and the redundancy field is a field for detecting and correcting errors within one word of a microinstruction. Register group 8 is a last-in, first-out stack of addresses and is used to store the return address when calling a subroutine.

When an address is stored in this register group 8, the contents of the first register 6, which serves as a stack pointer, is incremented by one, and after being read out, it is decremented by one.

When the second field 20 of the data set in the third register 15 is an INCSR instruction, the first selector 7 selects the signal line 108.
When issuing a CALL command, the signal line 110 is selected and the address set in the register group 8 is switched.

The second register 9 is a register that always holds the next address of the microinstruction currently being executed.
Its contents are incremented by adder 11. The second register 9 is therefore called a microprogram counter.

The second selector 10 is a selector for selecting the address of the RAM/ROM 12, and which of the plurality of signal lines 111, 113, and 114 is selected is determined by the second selector set in the third register 15.
is determined by the field 20 of.

It is clear from FIG. 5 that the contents of the second field 20 represent the instruction portion of the instruction. The third selector 13 is a selector for performing a conditional branch, and the third selector 13 is a selector for performing a conditional branch.
The second field 20 set to
At the time of the TEST instruction, depending on whether the state of the bit of the flip-flop group 17 selected by the third field 21 is 0 or 1,
Branch to either an adjacent even address or an odd address.

This specifies the address of the instruction to be executed in the next cycle.

The fourth selector 14 selects either the instruction code sent from the RAM/ROM 12 or the code corrected by the error correction circuit 16.
Select to set it in register 15 of

The third register 15 is a register for holding the microinstruction currently being executed.

The error correction circuit 16 is a circuit for correcting errors, and is a circuit for correcting errors in fields other than the ECC section of the third register 15, that is, the first to fourth fields 19.
If it is detected that there is an error in ~22,
The signal line 122 is used to indicate that the contents of the third register 15 are invalid.

The signals on the signal line 122 cause the first register 6, register group 8, second register 9, fourth register 24, and fifth register 25 to hold their contents.

In this case, the correctly corrected data is returned to the fourth selector 14 and set in the third register 15. Also, if there is no error, or even if there is an error, the fifth field 2 of the ECC section
If there is an error in No. 3, the above error correction operation is not performed.

The flip-flop group 17 is a collection of flip-flops for holding the states such as all 0s and overflows that occur as a result of operations, and the flip-flop group 17 is a set of flip-flops for holding the states such as all 0s and overflows that occur as a result of operations.
Only when the content of 0 is the TEST instruction, only one bit of the flip-flop group 17 is selected by the third field 21, and the signal line 126 and
The third selector 13 is switched via the fifth selector 18 and the signal line 125.

As a result, if the state of the signal on the signal line 125 is 0, the signal line 116 on the even address side is selected, and if it is 1, the signal line 116 on the odd address side is selected.
Select 17 to perform a conditional branch.

If the second field 20 is not a TEST instruction, the fifth selector 18 selects the signal line 124 side, and the lowest address of the RAM/ROM 12 is determined by the lowest bit of the second selector 10. become.

FIG. 8 and FIG. 9 are diagrams for explaining the operation of the above-mentioned circuit portion, and are diagrams analytically showing a microprogram and its execution timing chart.

Now, as shown in Figure 9, the microinstruction is
It is assumed that the data is stored in the RAM/ROM 12.

Assuming that the instruction at address 000 is executed first,
INCSR is executed, and as is clear from FIG. 5, the second selector 10 selects the signal line 113, the first selector 7 selects the signal line 108, and the content of the fourth field 22 is "001". The data is stored in the register group 8, the contents of the first register 6 become "001", and the process advances to the next address 001.

Address 001 is the TEST instruction, and the flip-flop group 17 selected by the third field 21
If the specific bit in 0 is 0, the third selector 13 selects the signal line 116, and the value of the least significant bit is 0.

Furthermore, since the second selector 10 selects the signal line 114 connected to the fourth field 22,
2+0→2, and the next cycle advances to address 002. Address 002 stores the RTN instruction, and “1” starting with INCSR is read from register group 8.
The second selector 10 selects the signal line 111 side.

So, next time I will fly to address 001.

Address 001 is the same TEST instruction as above, but
If, unlike the previous time, the value of the bit selected by the flip-flop group 17 is "001", then the sequence is 002+001→003, and the next step is to jump to address 003.
A BRH command is stored at address 003, and the second selector 10 selects the signal line 114 to access the fourth field 22. As a result, the next
Fly to address 006. Address 006 is a CALL command, in which the first selector 7 selects the signal line 110 side and stores the contents of the second register 9 in the register group 8. At the same time, the second selector 10 selects the signal line 114 side. As a result, next is 004
Fly to the address. The INC instruction is stored at address 004,
The second selector 10 selects the signal line 113 side. As a result, the next step is to proceed to address 005. At address 005
RTN instructions are stored in register group 8 as shown above.
Fly to address 007 where it was stored. At address 007
The INC instruction is stored, the next step is to jump to address 008, and so on, and so on.

During this time, the data path is controlled by other fields of the third register 15, and various calculations and data transfers are performed.

FIG. 10 shows the error correction circuit 16 in FIG.
FIG. 3 is a diagram showing in detail an example of the configuration of the device and its surroundings.

In FIG. 10, the subscript a indicates what belongs to the data part bits, and the subscript b indicates what belongs to the ECC part bits. In the error correction circuit 16, 2
A parity check circuit 7 performs a parity check between the ECC section and the data section.
28 is a syndrome decoder which receives the output of the parity check circuit 27 via a signal line 134 and outputs a signal indicating an erroneous bit from a combination of parity error signals to a signal line 135. It is.

29 is a data section error correction circuit for correcting errors in the data section.

The output signal line 123a is connected to the fourth selector 14.
The correct data is set in the third register 15 at the time of the correction selector.

30 checks whether an error exists based on the output of the syndrome decoder 28, and if an error exists, it is determined whether the error exists in the data part bits or the ECC part bits. This is a determination logic circuit for determining whether or not there is. If there is no error, or if there is an error but it is limited to the ECC part bits, the data on the signal line 120 is valid; if the contents of the data part bits 15a are incorrect, the data on the signal line 120 is valid.
A signal indicating that the above signal is invalid is sent to signal line 122.
Output on top.

In this specification, an example has been shown in which the present invention is applied to a control storage device of an information processing device that influences the performance of the entire device, but it goes without saying that the present invention can be applied to any other storage device having an error correction code.

(Effects of the Invention) As explained above, the present invention has a random access type RAM or ROM that has a data part and an ECC part in one word. A parity check circuit, a syndrome decoder, and a judgment logic circuit are provided to determine whether an error exists in the data section, and a data section error correction circuit is provided to correct the error only when an error exists in the data section. By providing a circuit, it is possible to omit the time required to correct errors in the ECC section, which account for 10 to 20% of one word in a memory device, and in the long run, the average access time is shortened and processing is made more effective. There is an effect that it can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a storage device equipped with an error correction circuit constructed according to a conventional method. FIG. 2 is a timing diagram showing the operation of FIG. 1. FIG. 3 is a block diagram showing one embodiment of a storage device according to the present invention. FIG. 4 is a diagram showing an example of the format of microinstructions for operating the storage device of FIG. 3. FIG. 5 is a diagram summarizing the operation of the instruction field in FIG. 4. FIG. 6 is a block diagram showing one embodiment of an arithmetic circuit controlled by the output of the storage device of FIG. 3. FIG. 7 is a timing diagram showing an example of the operation of the arithmetic circuit shown in FIG. FIG. 8 is a timing diagram showing an example of the operation in FIG. 3. FIG. 9 is a diagram showing an example of a microprogram for operating the storage device of FIG. 3. FIG. 10 is a block diagram showing an example of the configuration of an error correction circuit included in the storage device of FIG. 3. 1, 4, 6, 9, 15, 24, 25...Register, 2, 12...RAM/ROM, 3, 7, 10,
13, 14, 18...Selector, 5, 16...Error correction circuit, 8...Register group, 11...Adder, 17...
Flip-flop group, 19-23... Microinstruction internal field, 26... Arithmetic logic unit, 27
... Parity check circuit, 28 ... Syndrome decoder, 29 ... Data section error correction circuit, 30 ... Judgment logic circuit, 101-135 ... Signal line, 200-
207...Information.

Claims (1)

[Claims] 1 Random access type RAM for storing information that has a data part and an ECC part in one word
or a ROM, a register for holding the information read from the RAM or ROM, and an error correction circuit for detecting and correcting the error if there is an error in the content held in the register. and the error correction circuit includes a parity check circuit for performing a parity check on the data section and the ECC section, and a parity error signal combination based on the output of the parity check circuit. a syndrome decoder for outputting an indication signal of a bit in which an error has occurred; and a syndrome decoder for checking the presence of an error based on the output of the syndrome decoder to determine whether the error exists in the ECC section or a determination logic circuit for determining whether the error exists in the data section and instructing to correct only the error in the data section; and a data section error correction circuit for correcting the error in the data section and returning it to the register. A storage device characterized by being established.