JPH0135369B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a recovery processing method for a 1-bit error occurring in a control storage (CS) of a computer system that uses a pipeline control method.

[Problem that the invention seeks to solve]

The functions of computer hardware are being replaced by software, and such software is called firmware, and the actual situation is
It is a microprogram stored in CS. In a computer system that uses a pipeline control method,
Each instruction of the program is taken out one after another, each instruction is decoded, the address of the CS that stores the microprogram to execute it is determined, the CS is accessed by this address, and the read data (microstep) is stored in the register. However, if there is even a single bit error in this data, the desired control cannot be expected. Therefore, an ECC circuit is provided to correct 1-bit errors and detect 2-bit errors in data read from the CS.

However, if only error detection and correction is performed for the read error, the CS data will remain in error, so an error will occur each time the same microstep is read, and correction will be performed. Since error correction is limited to one bit, if one more bit becomes an error while the program is being executed in such a state, the error cannot be corrected and the operation will be interrupted. There are two types of bit errors: hard errors and soft errors.If it is a hard error, unless the CS is replaced,
It is unavoidable that an error occurs every time the faulty microstep is accessed, but if it is a soft error, it can be repaired by rewriting. Unless it is rewritten, it will not be repaired and will become the same as a hard error.

The present invention focuses on this point, and aims to improve reliability and durability by providing a collect cycle in the middle of pipeline processing to correct CS1 bit errors.

[Means for solving problems]

The present invention provides a data error recovery method for a control storage in a pipeline control computer system, in which a selector is provided between the control storage and a register, and error detection and correction of data in the register is performed.
An ECC circuit and a flip-flop that is set when there is an error in the data in the register are provided,
In the normal mode when the flip-flop is reset, the selector inputs the read data of the control storage to the register, and when the flip-flop is set, the selector enters the collect mode and inputs the collect data of the ECC circuit to the register. Furthermore, when the error is detected, the service processor fetches the address of the control storage at that time, rewrites the control storage with that address and correct data after executing a series of instructions, and The flip-flop is reset, and the control storage is rewritten a predetermined number of times or less, and if an error is detected even after rewriting more than the predetermined number of times, the control storage is not rewritten and the control storage is simply rewritten. This is characterized in that the register read data is only corrected by the ECC circuit and output.

[Effect]

The ECC circuit not only checks and corrects errors, but also rewrites the CS microsteps with correct data. In this way, soft errors can be completely recovered. In addition, if the number of rewrites is counted and the number exceeds a predetermined number, this is treated as a hard error and the rewrite is stopped, thereby avoiding unnecessary processing and time delays.
It is also effective in terms of maintenance if measures such as replacing the This will be explained in detail below with reference to illustrated embodiments.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, and 10 is a storage control section (S-
UNIT), 20 is a service processor (SVP),
The remaining parts are each part of the command control section 30. The instruction control unit 3 includes an instruction register 31 that receives instructions from the buffer (BUFF) 11 of the S-UNIT 10, a selector (SEL) 32 that decodes the instruction and converts it into a micro program address, and a Address register to maintain (ADRS)
33, a control storage section (CS) 34 that outputs the data (microstep) RD of the area specified by the address, a register 35 that holds the output data, and various control signals by the output of the register. A gate group 36 for selectively outputting is provided as standard. CS34 has S-
A pipeline control microprogram for executing part of the control by instructions from the UNIT 10, such as data selection when storing data in a register, is stored.

In this example, in addition to this, a selector 40 is interposed between the CS 34 and the register 35 to switch the data to the register 35 between the normal mode and the collect mode.
In the normal mode, the read data of the CS 34 is transmitted to the register 35, and in the collect mode, the data corrected (collected) by the ECC circuit 41 is transmitted to the register 35.
The ECC circuit 41 receives CS3 read out to the register 35.
Regarding the output data of 4, it has the function of correcting 1-bit errors and only detecting 2-bit errors, and when any error is detected, the output
Set the CS error flag 42 with ERR. This flag 42 is referenced by the SVP 20, and the CS address at the time of error occurrence is read from the address copy register 43 into a partial area of the counter 21 of the SVP 20. This is to rewrite the correct data WD to the corresponding address of CS34 later. In addition to this, a flip-flop (FF) 44 for mode switching is set when a 1-bit error is detected in the data in the register 35.
will be established. The FF 44 may be set by the 1-bit error detection output ERR of the ECC circuit 41, or by the error detection output of a parity check circuit (not shown) that detects parity errors from the input data RD of the register 35. In any case
When FF44 is set, it goes into collect mode,
The selector 40 selects the output (data with 1-bit error corrected) of the ECC circuit 41 CD. this
It is the reset signal RESET of SVP 20 that resets FF 44, which occurs after SVP 20 rewrites the correct data WD to CS 34.
When FF44 is reset, it goes into normal mode,
The selector 40 selects the output RD of the CS 34.

The operation of each mode will be explained below with reference to FIGS. 2 and 3. FIG. 2 is an explanatory diagram of the normal mode in which the FF 44 is reset. At this time, the selector 40 does not select the collect data CD of the ECC circuit 41, so the instruction pipeline within the instruction control unit 30 roughly follows the order of instruction register 31→address register 33→CS 34→register 35. In FIG. 2, i, B ₁ , . . . are each state in the pipeline instruction, i is the instruction fetch, and B ₁ and B ₂ are from the buffer 11 to the register 31.
D is the state where the command is taken in, D is the state where it is decoded by the selector 32, and R is the decoded state.
This is a state in which the CS address is transferred to the register 33.

On the other hand, in the collect mode shown in Figure 3,
The FF 44 is set, and the selector 40 selects the collect data CD of the ECC circuit 41. However, in the pipeline order, instruction register 31 → address register 33 → CS 34 → register 35 ₁ (first time of register 35) → ECC circuit 41 → selector 40 → register 35 ₂ (second time of register 35)
In that order. In this case, data from CS34
Selector 40 is also used when inputting RD to register ₃₅₁ .
is used (omitted in the drawing). still,
34' is shown for comparison with the CS in normal mode. The states in the pipeline instruction in Figure 3 include the state D one extra time, and a 1-bit error is detected after the first state D.
In state R, FF 44 is set. When a 1-bit error is detected, the first state D is canceled in the second state D, and the state returns to CS34 again.
Data read from and collected from
CD is set in register 35.

If you use the collect mode mentioned above, CS34
If it is a 1-bit error for each address (microstep), it is possible to correct it and execute the instruction. If the error is a soft error, rewriting will rewrite the correct data and return to the state without error. be able to. This CS rewriting is a pipeline process, so when the series of instructions that have already been read has been executed, the CPU is stopped and the SVP is rewritten.
Correct data WD to CS34 by 20 (this is
Rewrite the output CD of the ECC circuit 41. If this rewriting does not cause a 1-bit error at the same address, there is no need to shift to the collect mode which requires one extra cycle. However, if an error occurs even after performing this rewriting several times, there is a strong possibility that it is a hardware error in the CS34, so any further rewriting will be canceled (only the data will be collected by the ECC circuit 41). ). The number of writes is monitored by a counter in the SVP20, and the number of writes is monitored by a specified number (1
~N times), then stop.

〔Effect of the invention〕

As described above, according to the present invention, a CS rewrite cycle is provided in the middle of the pipeline of the computer that controls the pipeline, so even if there is a 1-bit error in the data read from the CS, it is returned to an error-free state. It has the advantage of being able to automatically recover and continue processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is an explanatory diagram of the normal mode, and FIG. 3 is an explanatory diagram of the collect mode. In the figure, 10 is a storage control section, 20
3 is a service processor section; 30 is an instruction control section; 3
1 is an instruction register, 34 is a control storage (CS), 35 is a register, 40 is a selector,
41 is an ECC circuit, and 44 is a flip-flop.

Claims (1)

[Claims] 1. In a control storage data error recovery method in a pipeline control computer system, the control storage 34 and the register 35
A selector 40 is provided between the registers, an ECC circuit 41 for detecting and correcting errors in the data in the register, and a flip-flop 44 that is set when there is an error in the data in the register, and in the normal mode when the flip-flop is reset. The selector inputs the read data RD of the control storage to the register, and when the flip-flop is set, the selector enters the collect mode and inputs the collect data CD of the ECC circuit to the register. The processor takes the current address of the control storage and stores that address and the correct data.
An error recovery processing method characterized by rewriting the control storage and resetting the flip-flop when a series of instructions has been executed in a WD. 2 Rewriting the control storage should not exceed a predetermined number of times, and if an error is detected even after rewriting more than the predetermined number of times, no rewriting will be performed, and the data read from the control storage will simply be ECCed.
2. The error recovery processing method according to claim 1, wherein the error recovery processing method is only corrected by a circuit and then output.