JPS59129995A - Storage device - Google Patents

Abstract

PURPOSE:To suppress the deterioration in accessing performance by discriminating a bit location where an error exists and correcting the error of a data section. CONSTITUTION:All bits except the least significant bit at an address corresponding to an RAM/ROM 12 are accessed by the output of a selector 10. Then, a parity check circuit 27, a syndrome decoder 28, and a discriminating logical circuit 30 discriminate whether a bit having an error of the RAM/ROM 12 having a data section and an ECC section in one word exists in the data section or the ECC section. Further, a data section error correcting circuit 29 is provided so as to correct the error only when the error exists in the data section so as to omit the time correcting the error of the ECC section in one word of the storage device.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a storage device, and particularly to an error correction method thereof.

(Prior Art) Conventional information processing devices use error correction codes such as Hamming codes. A storage device with a correction function is used, and this is configured as shown in FIG.

In FIG. 1, an example of a storage device is an address register 1.
, a RAM or ROM 2 , a selector 3 , a data register 4 , and an error correction circuit 5 .

In FIG. 1, address register 1 and data register 4 each operate in synchronization with a clock signal.
One word of data whose address is the contents of the first address register 1 is read from the RAM or ROM 2, passed through the selector 3, and set in the data register 4.

The output of the data register 4 is transferred to other devices that require the data, but is also applied to the error correction circuit 5 at the same time.

If there is an error in the contents of the data register 4, the error is detected and corrected before being returned to the selector 3. Further, a signal line 105 is provided to notify other devices whether or not there is an error in the data on the output signal line 104.

Next, an example of the operation of the circuit shown in FIG. 1 will be explained in detail with reference to the timing chart shown in FIG.

The state of the signal on the output signal line 101 from the address register 1 indicates address 200 at clock timing t1. One word of data from address 200 of the RAM or ROM 2 is passed through the register 3 and set in the data register 4 at the next clock timing t2.

At clock timing t2, data register 4
The error correction circuit 5 detects whether or not the data set in the data contains an error. If no error exists, the state of the signal on output signal line 105 is a logical 0, and the device receiving the signal on output signal line 104 recognizes that data 204 is valid.

At clock timing t2, the data on the output signal line 101 from the address register 1 indicates the address of address 201.

Data 205 stored at address 201 is set in data register 4 during m of clock timing t3 in the same manner as described above. At this time, if it is assumed that an error has been detected in the error correction circuit 5, the state of the signal on the output signal line 105 is a logic value 1, and the data 205 on the output signal line 104 is an error code. Other devices will know that it is invalid.

fA') The correction circuit 5 correctly corrects the data 205 to become data 206, and directs the selector 3 to the signal line 106 side. Therefore, correct data 206 is set in the data register 4 at clock timing t4t.

At clock timing t4, the data set in the data register 4 is correct, so the state of the signal on the output signal line 105 becomes a logical value O.

Note that when moving from clock timing t3 to clock timing t4, the contents of address register 1 are held so as not to change. After that, clock timing t4,
L! Since the data set in the data register 4 is correct at time i, the same operation as at clock timings t1 and t2 is performed. However, in this method, when errors are detected by the error correction circuit 5, even errors in the ECC section of one word or less are handled and corrected in the same way as errors in other information bits. .

Therefore, if there is a fault in the word direction in the ECC section, a correction cycle such as clock timing L3 in FIG. 2 is inserted when reading data, and clock timings t3 and t4 are alternately repeated. It's not going to happen,
The drawback was that it was only actually working effectively half of the time.

(Objective of the Invention) An object of the present invention is to detect whether an error exists in the data section, or whether an error exists in the data section in a random access type RAM or ROM that has a data section and an ECC section in one word. A parity check circuit, a syndrome decoder, and a determination logic circuit are provided to determine whether an error exists in the ECC section added for correction, and the error is corrected only when an error exists in the data section. It is an object of the present invention to provide a storage device equipped with an error correction circuit configured to solve the above-mentioned drawbacks and suppress deterioration in access performance by providing a data section error correction circuit.

(Structure of the Invention) A storage device according to the present invention includes at least a RAM/ROM, a register, and an error correction circuit, and the error correction circuit includes a parity check circuit, a syndrome decoder, a judgment logic circuit, and a data part error correction circuit. It consists of a correction circuit.

几AM/ROM is a random access type memory for storing information having an ECC part and a data part in one word.

The register is a circuit for holding information read from the RAM/1tOM.

The error correction circuit is a circuit that detects and corrects the error υ when there is an error in the contents held in the register.

The parity check circuit that constitutes the error correction circuit is a circuit that performs a parity check according to the number of bits in the E'3CC section.

The syndrome decoder is a circuit that receives the output of the parity check circuit and outputs a signal indicating a pit in which an error occurs based on a combination of parity error signals.

The judgment logic circuit checks the existence of an error based on the output of the syndrome decoder, determines whether the error exists in the ECC section or the data section, and corrects only the error in the data section. This is a circuit for instructing.

The data section error correction circuit is a circuit that corrects errors in the data section and returns them to the register.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 3 shows an embodiment of a storage device according to the present invention.

FIG. 3 shows an example of a control storage device of an information processing system, in which registers 6.9.15 of first to fang 3 and selectors 7.10.13.14.18 of first to fang 5 are shown. , register group 8, adder 11, RAM/ROM 12,
It is equipped with an error correction circuit 16 and a flip-flop group 17.

The operation of the storage device will be explained below according to FIG.

In FIG. 3, microinstructions are stored in the ROM 12.

According to the output of the second selector 10, fi, RAM/ROM1
The least significant bit (LSB) at the corresponding address of 2
) are accessed.

Whether the value of the least significant bit is 0 (the value appearing on the data signal line 116) or 1 (the value appearing on the data signal line 117) depends on the output of the fifth selector 18. By selector 13 of f3! It is configured so that ll1 is selected.

The selected 1-word microinstruction is sent to the fourth selector 1.
4 to the third register 15. This microinstruction is composed of fields 19 to 23 of first to fang 5 as shown in FIG.

Field 19 of field 1 is a field for controlling the data bus. For example, Figure 6 is a diagram showing an example of a data bus, and the fourth and fifth registers 24.2
5 and the arithmetic logic unit (AL'U) 26.

The first field 19 is the fourth and fifth register 2
4.25 write signals and arithmetic logic unit 26
It controls the operation mode signal for
(Fourth register 24) (Fourth register 24) - (Fifth register 25) → (
fifth register 25).

The second field 2o is a field that represents an instruction for controlling the operation sequence of the RAM/ROM 12.

The third field 21 is used to select the bit to be read when the second field 2o is a TENT instruction as shown in FIG.

The fourth field 22 is a field for setting branch destination addresses, calculation constants, and the like.

The fourth field 23 is a redundancy field, and the redundancy field is a field for detecting and correcting errors in one word of a microinstruction. Register group 8 is a last-in, first-out stack of addresses and is used to save the return address when calling a subroutine.

When an address is stored in this register group 8, the contents of the first register 6, which serves as a stack pointer, is incremented by 1, and after being read out, it is decremented by 1.

When the second field 20 of the data set in the register 15 of the fangs 3 is an INC3R command, the first selector 7 selects the signal line 108, and when it is a CALL command, the first selector 7 selects the signal line 110 and sends the data to the register group 8. The address to be set is being changed.

The second register 9 always holds the next address of the microinstruction currently being executed, and its contents are incremented by the adder U.

The second register 9 is therefore called a microprogram counter.

The second selector 10 is a selector for selecting the address of the AM/ROM 12, and is a selector for selecting the address of the plurality of signal lines 111.
Which of 113 and 114 is selected is determined by the second field 20 set in the third register 15.

It is clear from FIG. 5 that the contents of the second field 20 represent the instruction part of the instruction.

The third selector 13 is a selector for performing a conditional branch, and when the second field addition set in the third register 15 is a TEST instruction, the flip-flop selected by the third field 21 is selected. Group 17
Depending on whether the state of the bit is 0 or 1, a branch is made to either an adjacent even address or an odd address.

This specifies the address of the instruction to be executed in the next cycle.

The fourth selector 14 selects either the instruction code sent from the RAM/ROM 12 or the code corrected by the error correction circuit 16 to be set in the register 15 of the fan 3.

Register 15 of E.3 is a register for holding the microinstruction currently being executed.

The error correction circuit 16 is a circuit for correcting errors,
If it is detected that there is an error in fields other than the ECC part of the third register 15, that is, the first to fourth fields 19 to 22, the contents of the third register 15 are invalid. This is shown using a signal line 122.

According to the signal on the signal line 122, the first register 6, the register group 8, the second register 9, and the fourth register 2
4 and the fifth register 25 hold the contents.

In this case, the correctly corrected data is transferred to the fourth selector 1.
4 and set in the third register 15. Also, if there is no error, or even if there is an error,
If an error exists in the fifth field 23 of the CC section, the above error correction operation is not performed.

The flip-flop group 17- is all O generated as a result of the operation.
It is a collection of 7 lip-flops for holding states such as overflow and overflow, and only when the contents of the second field 20 set in the third register 15 is a TEST instruction, the third field 21 Only one bit of the flip-flop group 17 is selected, and the third selector 13 is switched via the signal line 126, the fifth selector 18, and the signal line 125.

As a result, if the state of the signal on the signal line 125 is O, the signal line 116 on the even address side is selected, and if it is 1, the signal line 117 on the odd address side is selected, and a conditional branch is performed. .

If the second field 20 is not an 'I' E S '1' instruction, the fifth selector 18 selects the side of the signal line 124, and the least significant bit of the selector 10 of )12 selects the RAM/)10M42. The lowest address will be determined.

8 and 9 are diagrams for explaining the operation of the above-mentioned circuit portion, and are diagrams analytically showing a microprogram and its execution timing chart.

Now, as shown in Figure 9, the microinstruction is RAM/approximately 0.
Assume that it is stored in M12.

If the instruction at address 000 is executed first, lN
C3R is executed, and as is clear from FIG. 5, the selector 10 of fang 2 selects the signal line 113, and the selector 7 of fang 1
selects the signal line 108, the content "001" of the fourth field 22 is stored in the register group 8, the content of the first register 6 becomes "001", and the process advances to the next address 001.

Address 001 is the TEST instruction, third field 2
Flip-flop selected by 1! If the specific bit in J17 is O, selector 1 of C3
3 selects the signal line 116, and the value of the least significant bit is 0.

Furthermore, the second selector 10 selects the signal line 114 connected to the fourth field 22, so 2+0→2, and the next cycle proceeds to address 002. Address 002 stores R and TN instructions, and register group 8 stores l.
11″ starting with NC3R is read out, and selector 1 of fang 2
0 selects the signal line 111 side.

So, next time I will fly to address 001.

Address 001 is the same TEST instruction as above, but unlike the previous time, if the value of the bit selected by the flip-flop group 17 is "001", then 00
2+001 → 003, and next it flies to address 003.
A BRH command is stored at address 003, and the second selector 10 selects the signal line 114 to access the field 22 of 'A-4. As a result, the next step is to jump to address 006. Address 006 is a CALL instruction, in which the first selector 7 selects the signal line 110 side and stores the contents of the second register 9 in the register group 8. At the same time, the second selector 10 selects the signal line 114 side. As a result, the next destination is address 004. An INC command is stored at address 004, and the second selector 10 selects the signal line 113 side. As a result, the next step is to proceed to address 005. The TN instruction is stored at address 005 and jumps to address 007, which was stored in register group 8 as described above. The INC instruction is stored at address 007, and the next one is 008.
The sequence of instructions progresses, such as jumping to an address.

During this time, the data bus is controlled by other fields of the third register 15, and various operations and data transfers are performed.

FIG. 10 is a diagram showing in detail one embodiment of the configuration of the error correction circuit 16 and its surroundings in FIG. 3.

In FIG. 10, the subscript "a" indicates what belongs to the data section bit, and the subscript "su" indicates what belongs to the BCC section pint. In the error correction circuit 16, a parity check circuit 27 performs a parity check according to the number of bits of ECC sound B (7). 28 is a syndrome decoder, which receives the output of the parity check circuit 27 via a signal line 134, and outputs a signal indicating the bit in which an error has occurred from the combination of the parity error signals 1 to the signal (, 113s). It is a decoder for

Reference numeral 29 denotes a data tone 5 error correction circuit for correcting errors in the data section.

The output signal line 123a is returned to the selector 14 of the tooth 4, and correct data is set in the third register 15 during the correction cycle.

30 checks whether there is an error based on the output of the syndrome decoder 28, and if there is an error, it is determined whether the error exists in the data part bits or the ECC part bits. This is a determination logic circuit that determines whether the If there is no error, or if there is an error but it is limited to the ECC part bits, the data on the signal line 120 is valid, and if the contents of the data part (Pi) 15a are incorrect, the signal line 120
A signal indicating that the above signal is invalid is output onto the signal line 122.

In this specification, an example is shown in which the present invention is applied to a control storage device of an information processing device that influences the performance of the entire device, but it is needless to say that the present invention can be applied to any other storage device having an error correction code.

(Effects of the Invention) As explained above, the present invention has a random access type [(A M
In order to determine whether the bit in which the error occurred is in the data section or the ECC section, the R, OM is provided with a parity check circuit, a syndrome decoder, and a judgment logic circuit. Incorrect υ in data section
By providing a data section ib correction circuit that corrects errors only when errors exist, the time required to correct errors in the ECC section, which accounts for 10 to 20% of one word in the storage device, can be omitted. This has the effect that, in the long run, the average access time can be shortened and processing can be performed more effectively.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a storage device equipped with an error correction circuit constructed according to a conventional method. Figure 2 is a diagram showing the timing of the operation of figure f1. FIG. 3 is a block diagram showing an embodiment of the storage device according to the present invention. -f4 is a diagram showing an example of the format of a microinstruction for operating the storage device of FIG. 3. FIG. 5 is a diagram summarizing the operation of the command field in the Fang 4 diagram. FIG. 6 is a block diagram showing an embodiment of an arithmetic circuit controlled by the outputs of the storage devices shown in FIGS. 2 and 3. The OFF diagram is a timing diagram showing an example of the operation of the arithmetic circuit shown in FIG. FIG. 8 is a timing diagram showing an example of the operation in FIG. 3. , f9 is a diagram showing an example of a microprogram for operating the storage device of FIG. 3. FIG. 10 is a block diagram showing a configuration example of an error correction circuit included in the storage device of FIG. 3. 1.4.6.9.15.24.25...Register 2.
12...几AM/几OM 3.7.10.13.14.18...Selector 5.1
6...Error correction circuit 8...Register group 11...Adder 17...
Fritub flow rough groups 19 to 23...Microinstruction internal field 26...
- Arithmetic logic unit 27... Parity check circuit 28... Syndrome decoder 29... Data part error correction circuit 30... Judgment logic circuits 101-135... Signal lines 200-207... Information patent application Person: NEC Co., Ltd. Agent, Patent Attorney Ii 〕 Ro Hisashi Figure 1 Figure 2 Figure 10 Figure 23a

Claims (1)

[Claims] Random ACMOS type RAM''! or RO for storing information having a data part and an ECC part in one word.
M, a register for holding the information read from the RAM or ROM, and an error correction circuit for detecting and correcting the error if there is an error in the content held in the register. and a parity check circuit for the error correction circuit to perform a parity check of a method according to the number of bits of the ECC section; a syndrome decoder that outputs an instruction signal for a bit in which an error has occurred;
Checking the presence of an error based on the output of the syndrome decoder, determining whether the error exists in the ECC section or the data section, and correcting only the error in the data section. 1. A storage device comprising: a determination logic circuit for instructing the data section; and a data section error correction circuit for correcting errors in the data section and returning them to the register.