JPS61110247A - Storage device - Google Patents

Abstract

PURPOSE:To improve the storing performance of a storage device, by operating the storage device by extending the cycle time only when the error of a byte which is not designated for writing occurs at the time of partial writing operations. CONSTITUTION:When a 1-bit error controlling signal on a signal line 26 is '1', a cycle time is extended. Namely, read out data which are corrected by a correction circuit 17 and sent onto a signal line 37 are selected by the 2nd selector 18. Read out data on a signal line 38 or writing data on a signal line 28 are selected by the 1st selector 9. The writing data on the signal line 28 are selected as a byte to which writing is designated and the read out data on the signal line 38 are selected as a byte to which writing is not designated. Selected data on a signal line 29 and a check bit on a signal line 30 are written in a memory matrix circuit 11 at a timing delayed from the timing at the time of no error.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory device that can extend the cycle time only when a 1-bit error occurs, and particularly relates to a control method during a partial write operation.

(Prior Art) FIG. 3 is a block diagram showing an example of a storage device according to the prior art, which is configured to extend the cycle time only when a 1-bit error occurs. In FIG. 3, 1 is a control circuit, 5 is a first register, 6 is an address control circuit, and TV! buffer, 8 is a second register, 9 is a first selector, 10 is a check bit generation circuit, 11 is a memory matrix circuit, 12 is a third register, 13 is a syndrome generation circuit, 14 is a byte decoder, 15 is a bit 16 is an AND gate, 1T is a correction circuit, 1B is a second selector, and 43 is a parity checker.

Conventionally, when a partial write operation is executed in a storage device configured such that the cycle time can be extended only when a 1-bit error occurs, the signal line 31 from the memory matrix circuit 11 as shown in FIG. When there is a bit error in read data ll'C1, a syndrome is generated from the syndrome generation circuit 13 onto the signal line 33, the syndrome is input from the signal line 33 to the parity checker 43, and the syndrome is checked by the parity checker 43. A 1-bit error signal is sent on signal line 44. The 1-bit error signal on the signal line 44 is input to the control circuit 1, and is sent to various timing signals and the signal line 21.
The above control signal is generated at a later timing than when there is no error. That is, the read data corrected by the correction circuit 17 is input to the selector 1B via the signal line 37, and is selected by the second selector 1B. Read data of bytes without write designation is output from the signal line 3B and input to the first selector 9. Next, the first selector 9 selects the write data of the designated write byte on the signal line 28, and combines the write data on the signal 1s29 with the check bit generated by the check bit generation circuit 10 and sent out on the signal line 30. The bits are written to the memory matrix circuit 11 using a write enable signal whose timing is delayed.

(Problem to be Solved by the Invention) Therefore, in a storage device configured to extend the cycle time only when a 1 write error occurs, even if a partial write operation is executed, the read data IC1
A problem has arisen in that when a bit error occurs, the cycle time must be extended as in the read operation.

The purpose of the present invention is to prohibit the generation of a 1-bit error control signal when a 1-bit error occurs in a write-designated byte during a partial write operation, and generate a 1-bit error control signal when an error occurs in a byte that is not a write-designated byte. It is an object of the present invention to provide a memory device configured to eliminate the above-mentioned drawbacks and extend the cycle time only when a 1-bit error occurs.

(Means for Solving the Problems) A storage device according to the present invention is capable of executing write/read operations in response to write/read instructions from an arithmetic processing unit, and has a 1-bit error correction function, It is configured so that when a read data IC 1-bit error occurs, the operation can be executed with a longer cycle time than in a normal cycle without an error, and includes a byte decoder means, a plurality of logical product means, and a logical sum means. It is constructed by comprising the following.

The byte decoder means are for decoding read data bytes containing one bit errors due to generated syndromes.

This is for calculating the AND of the error byte designation signal for a 1-bit error, the write byte designation signal, and the partial write designation signal for each read data byte.

The OR means prohibits the generation of a 1-bit error control signal when a 1-bit error occurs in a write-designated byte during a partial write operation, and prohibits the generation of a 1-bit error control signal when an error occurs in a byte for which writing is not designated. This is for calculating the logical sum of the outputs of a plurality of logical product means to generate a bit error control signal.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention. In Figure 1, the same numbers as in Figure 2 refer to
The same elements as those in the figure are shown, except that 2 is a NAND gate, 3 is an AND gate, and 4 is an OR gate.

In FIG. 1, in the case of a partial write operation, the signal line 39
The upper address is sent to the memory matrix circuit 11 via the first register 5, address control circuit 6, and buffer 7.
, the read data is read out from the memory matrix circuit 11 onto the signal line 31, and the read data is read out from the memory matrix circuit 11 onto the signal line 31.
is set to If there is a 1-bit error in the read data on signal #31, a syndrome is generated by syndrome generation circuit 13 and sent onto signal line 33. Therefore, a C error byte designation signal is generated from the byte decoder 14 on the signal line 34, and it becomes clear in which byte a 1-bit error has occurred. On the other hand, by negating the AND of the byte designation signal on the signal line 22 and the partial write designation signal on the signal line 23, only the designated byte is sent to the signal line 24 at the time of the partial write operation. Set the partial write byte designation signal to @0#. When a byte is not specified in a partial write operation, or when the partial write byte designation signal is not specified for a partial write operation, the partial write byte designation signal on the signal 124 is set to '1'.

The error byte designation signal sent from the NAND gate 2 onto the signal line 34 and the partial write byte designation signal on the signal line 24 are ANDed by an AND gate 3 and output to the signal line 25. The AND signal of the byte input from the signal line 25 to the OR game) 4 and the (NAND+
A logical sum is calculated with the AND signal of another byte inputted from the AND) system to the OR gate 4, and a 1-bit error control signal is generated on the signal line 26.

That is, in the case of a partial write operation, if there is a 1-bit error in the write-designated byte, the partial write byte designation signal on the signal line 24 is ``0#'', so there will be a 1-bit error on the signal line 26. The control signal becomes 10''. If there is a K1 bit error (Pi for which writing is not specified),
The partial write byte designation signal on signal line 24 becomes 11#, and the error byte designation signal on signal 1fs34 becomes @1'.
Therefore, the 1-bit error control signal on the second signal line becomes @1''K.

Figure 3 shows a gate circuit (NAND+AN) that generates a 1-bit error control signal when data is specified as 4 bytes.
A block diagram of D) is shown. In Figure 3, 202-2
04 are NAND gates, and 302 to 304 are AND gates. When the 1-bit error control signal on the signal line 26 is “0,” the operation ends in a cycle when there is no 1-bit error in the read data.In other words, the uncorrected data output from the register 12 Selected by the second selector 18. The selected read data on the signal line 38 or the second
The write data input to the register 8 is selected by the second selector 9. The write data on the signal line 2B is selected as the write-designated byte, and the read data on the signal line 38 is selected as the non-write-designated byte. At this time, since a 1-bit error has occurred in the write-designated byte, read data with a 1-bit error will not be selected.

The selected data on the signal line 29 and the check bit generated by the check bit generation circuit 10 and sent out on the signal line 30 are written into the memory matrix circuit 11.

When the 1-bit error control signal on signal line 26 is @1'', the cycle time is extended.
The read data corrected by T and sent onto the signal line 3T is selected by the second selector 1B. Selected read data on signal line 3B or signal line 2
The write data on 8 is selected by the first selector 9. The write data on the signal line 28 is selected as the byte designated to be written, and the read data on the signal line 38 is selected as the byte not designated to be written.

The selected data on the signal line 29 and the check bit on the signal line 30 are written to the memory matrix circuit 11 at a timing later than when no error occurs.

(Effects of the Invention) As explained above, the present invention prevents the cycle time from being extended when there is a 1-bit error in the read data of a byte designated for writing in a partial write operation, but the cycle time is not extended when there is a 1-bit error in the read data. By extending the cycle time and operating only when a problem occurs, there is an effect that storage performance can be easily improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention. FIG. 2 is a block diagram showing in detail a portion of the storage device shown in FIG. 1. FIG. 3 is a block diagram showing an embodiment of a storage device according to the prior art. 1...Control circuit 2.202~204...NAND gate 3.302~
304.16...AND gate 4... -OR gate 5.8.12...Register 6...Address control circuit T----Buffer 9.18...-Selector 10...Check bit generation circuit 11...Memory matrix circuit 13...Syndrome generation circuit 14...Byte decoder 15...Bit decoder 17...Correction circuits 19-4j, 2202-2204.2402-2404
．． 2502-2504.3402-3404...Signal line

Claims (1)

[Claims] It can execute write/read operations in response to write/read instructions from the processing unit and has a 1-bit error correction function. In a storage device capable of performing operations with an extended cycle time, byte decoder means for decoding a read data byte containing a 1-bit error due to a generated syndrome; a plurality of AND means for calculating the logical product of the error byte designation signal, the write byte designation signal, and the partial write designation signal; and 1 bit if the 1 bit error occurs in the write designation byte during the partial write operation To obtain the logical sum of the outputs of the plurality of AND means so as to prohibit the generation of the error control signal and generate the 1-bit error control signal when an error occurs in the byte for which writing is not specified. What is claimed is: 1. A storage device comprising a logical sum means.