TW202109545A - Memory apparatus and data accessing method thereof - Google Patents

Abstract

The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.

Description

Memory device and its data access method

The present invention relates to a memory device and its data access method, and more particularly to a memory device with multiple error correction code (ECC) mechanisms.

In the prior art, for non-volatile memory, for example, the ECC mechanism for BCH operation can run on each codeword. However, in statistics, most codewords only require zero or a small number of correction bits. That is to say, in the conventional technology, since there is only one ECC mechanism, even if most codewords do not need this, the memory device always uses the highest power to read or write each codeword. In addition, in the conventional technology, even if most codewords do not need this, the parity check bit still needs to be switched for the maximum number of times for a single ECC mechanism.

The invention provides a memory device for reducing operating power and a data access method thereof.

The data access method of the present invention includes: performing a read operation on the memory device based on the address information to obtain a codeword and an indicator, wherein the indicator corresponds to the codeword; making the first error correction code (ECC) operation or the first error correction code (ECC) operation or the second Two ECC operations run on the codeword to generate error correction data, wherein the first ECC operation corrects fewer bits than the second ECC operation.

The invention also provides a memory device including a memory cell array and a controller. The controller is coupled to the memory cell array and configured to execute the above data access method.

Based on the above, the present invention enables one of the first ECC operation and the second ECC operation according to the number of error bits of the message bit of the codeword. In other words, it is not necessary to use the maximum power to run the ECC operation on each codeword, which can save the power consumption of the memory device.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Referring to FIG. 1, the data access method in FIG. 1 is adapted to a memory device, and the memory device may be a non-volatile memory, such as a flash memory. Step S110 performs a read operation on the memory device based on the address information to obtain codewords and instructions. In detail, before performing a read operation, a data access command with address information can be received by the memory device. Then, the read operation can be performed on the memory device based on the address information. In this embodiment, based on the address information, the indicator can be pre-stored in the memory device. In addition, the code word read by the read operation includes multiple message bits and multiple parity check bits.

In step S120, according to the indicator, the first error code (ECC) operation or the second ECC operation is executed on the code word to generate error correction data, wherein the first ECC operation corrects fewer bits than the second ECC operation. In detail, one of the first ECC operation and the second ECC operation can be initiated according to the indicator. For example, the indicator may be a digital signal with one bit. In this embodiment, if the indicator is at the first logic level, the first ECC operation with less error bit correction capability can be activated; and if the indicator is at the second logic level, the belt replacement can be activated. The second ECC operation with multiple error bit correction capability. The first logic level is complementary to the second logic level. The first logic level can be a logic level 1 and the second logic level can be a logic level 0.

In the embodiment of the present invention, the indicator can be set according to the number of possible error bits of the corresponding codeword, and is pre-stored in the memory device based on the address information. If the number of error bits of the corresponding codeword is less than the preset reference, the indicator can be set to the first logic level; and if the number of error bits of the corresponding codeword is not less than the preset reference, the indicator can be set to the second Logic level.

It can be seen here that in the embodiment of the present invention, an appropriate ECC operation is started for each codeword. In other words, the memory device does not need to always perform the ECC operation on the codeword with the maximum power. It can save the power consumption of the memory device.

Referring to FIG. 2, the code word CW and the corresponding indicator IND can be read based on the address information ADD. The code word CW may include multiple message bits and multiple parity check bits.

On the other hand, the logic level of the indicator IND can be checked. If the indicator IND is a logic level 1, the first ECC operation (ECC1) 210 can be started to run on the code word CW. In this embodiment, for example, the first ECC operation 210 may be performed by a first ECC encoder (the first ECC encoder may have 4 groups), and the first ECC operation 210 may be based on the Hamming (12, 8) code To run.

Conversely, if the indicator IND is at a logic level of 0, the second ECC operation (ECC2) 220 can be started to run on the code word CW. In this embodiment, for example, the second ECC operation 220 may be performed by a second ECC encoder, and the second ECC operation may be performed based on the BCH (50, 32) code.

In this embodiment, the first ECC operation corrects fewer error bits than the second ECC operation, and the memory device performs the first ECC operation consumes less power than the second ECC operation.

The memory device further outputs the error correction data ECD by selecting the output of the first ECC operation 210 or the output of the second ECC operation according to the indicator IND. In detail, if the indicator is the logic level 1, the output of the first ECC operation 210 can be selected to generate the error correction data ECD. Conversely, if the indicator is a logic level of 0, the output of the second ECC operation 220 can be selected to generate the error correction data ECD.

When accessing multiple codewords, the memory device can adaptively select an appropriate ECC operation to run on each codeword. It can save the power consumption of the memory device.

Please note here that in some embodiments, at least one third ECC operation can be added to the data access process. The third ECC operation can correct more error bits than the second ECC operation 220. In this case, the indicator IND may have 2 bits. For example, if the indicator is the logic level 00, the second ECC operation can be started; if the indicator is the logic level 01, the first ECC operation can be started; and if the indicator is the logic level 10, then the Start the third ECC operation. Of course, the relationship between the indicator and the activated ECC operation can be defined by the designer of the memory device, and there is no special restriction here.

In this embodiment, the output data size of the second ECC operation 220 may be 4 bytes, and the output data size of the first ECC operation 210 may not be larger than 4 bytes.

Referring to FIG. 3, step S310 receives a write command from the memory device. Next, in step S320, a pre-reading process is performed on the memory device. In the pre-reading process, the read operation can be performed based on the address information of the write command, and the indicator IND can be obtained through the pre-reading process. Step S330 determines whether the indicator IND is the logic level 1, and if the indicator IND is not the logic level 1, keep the indicator logic level 0 and execute step S352. Conversely, if the indicator IND is a logic level 1, the read codeword that has passed the pre-read operation can be checked through the write verification read flow, and the number of error bits can be checked in step S340. In the write verification read process, the written code word written in the memory device is read, and the read code word is compared with the written code word of the write verification read process.

If the number of error bits is equal to 0, the indicator IND remains at the logical level 1, and step S351 is executed. Conversely, if the number of error bits is not equal to 0, the indicator IND is adjusted to the logic level 0, and step S352 is executed. When the indicator IND is the logic level 1, step S351 enables the first ECC operation (ECC1) based on the Hamming (12, 8) code. When the indicator IND is the logic level 0, step S352 enables the second ECC operation (ECC2) based on the BCH (50, 32) code.

After the execution of step S351 or step S352 is completed, a plurality of updated message bits and a plurality of updated parity check bits can be generated, and the updated message bits and the updated parity check bits form an updated codeword UCW. Based on the address information of the write command, the updated code word UCW and the corresponding indicator IND can be written into the memory device. The data writing operation can be completed.

Here, since the indicator IND will be written only once (no loop problem), the first write pulse for writing the indicator IND into the memory device can be provided, and it can be used during the write operation. In the second write pulse for writing the updated codeword UCW into the memory device, the first write pulse is different from the second write pulse.

It should be noted here that when the updated message bit and the updated parity check bit are written into the memory device, the updated message bit and the updated parity check bit can be combined with multiple original message bits and A plurality of original parity check bits are compared, and the updated message bit and the updated parity check bit can be written based on a less bit change mechanism. The original message bit and the original parity check bit can be obtained through the pre-read operation in step S330. The less bit change mechanism can be implemented by a mechanism well known to those skilled in the art. The less bit change mechanism can reduce the number of memory cells that are programmed for each data writing operation.

Referring to FIG. 4, step S410 receives a write command from a memory device with address information. Next, step S420 performs a pre-reading process on the memory device. In the pre-reading process, the read operation can be performed based on the address information of the write command, and the indicator IND can be obtained through the pre-reading process. Step S430 determines whether the indicator IND is the logic level 0, and if the indicator IND is not the logic level 0, then step S440 is executed. Conversely, if the indicator IND is at a logic level of 0, step S480 is executed.

In step S440, if the number of error bits is greater than 0, step S450 is executed to enable the first ECC operation (ECC1) based on the Hamming (12, 8) code. If the number of error bits is not greater than 0, step S460 is executed.

In step S460, a write verification read process is performed. In step 460, the written code word written in the memory device is read, and the read code word is compared with the written code word used in the write verification read process. If the read code word and the write code word are the same, the write command has been completed. Conversely, if the read codeword and the written codeword are different, step S480 is executed.

In step S480, the indicator IND is set to a logic level of 0, and the second ECC operation (ECC2) is enabled for the ECC operation based on the BCH (50, 32) code. The second ECC operation can correct more error bits than the first ECC operation. It can ensure the accuracy of the codeword.

After performing step S450 or step S480, a plurality of updated message bits and a plurality of updated parity check bits may be generated, and the updated message bits and the updated parity check bits form an updated codeword UCW. Based on the address information of the write command, the updated code word UCW and the corresponding indicator IND can be written into the memory device. The data writing operation can be completed. It should be noted here that when the updated message bit and the updated parity check bit are written into the memory device, the updated message bit and the updated parity check bit can be based on the less bit changes mentioned above Mechanism write.

Referring to FIG. 5, the memory device 500 may be a non-volatile memory. For example, the memory device 500 may be a flash memory. The memory device 500 includes a memory cell array 510 and a controller 520. The memory cell array 510 includes a plurality of memory cells. The controller 520 is configured to execute the steps of the data access method mentioned in the previous embodiment. The detailed operations of the steps have been described in the above embodiments, and the description will not be repeated here.

Regarding the controller 520. The controller 520 may be a processor having a computing function. Alternatively, the controller 520 can also be a hardware circuit designed by using a hardware description language (HDL) or any digital circuit design method well known to those skilled in the art, and can be programmed through a field programmable gate array (field It can be realized by programmable gate array; FPGA, complex programmable logic device (CPLD) or application-specific integrated circuit (ASIC).

In summary, the power consumption of the memory device can be reduced by selecting an appropriate ECC operation for each codeword. In addition, by using a less bit change mechanism to write codewords, the power consumption of the memory device can be further reduced, and the service life of the memory cell (ie, flash memory storage unit) can be increased.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

210: First ECC operation 220: Second ECC operation 500: Memory device 510: Memory Cell Array 520: Controller S110, S120, S310, S320, S330, S340, S351, S352, S410, S420, S430, S440, S450, S460, S470, S480: steps ADD: address information CW: codeword ECD: Error correction data IND: indicator UCW: updated codeword

FIG. 1 shows a flowchart of a data access method according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a data access method according to another embodiment of the present invention. FIG. 3 is a schematic diagram of a data access method according to another embodiment of the present invention. FIG. 4 is a schematic diagram of a data access method according to another embodiment of the present invention. FIG. 5 is a block diagram of a memory device according to an embodiment of the invention.

S110~S120: steps

Claims (16)

A data access method for a memory device includes: Performing a read operation on the memory device based on the address information to obtain a codeword and an indicator, wherein the indicator corresponds to the codeword; and Causing the first error correction code operation or the second error correction code operation to run on the codeword for generating error correction data, Wherein, the first error correction code operation corrects fewer bits than the second error correction code operation. According to the data access method described in item 1 of the scope of patent application, the indicator is set according to the number of error bits of the codeword during the write verification and read process. According to the data access method described in item 1 of the scope of patent application, the codeword includes a plurality of message bits and a corresponding plurality of parity check bits, and the data access method further includes: Receiving a data write command based on the address information; Checking the number of error bits of the codeword during the pre-reading and writing verification read process to obtain a check result; Set the indicator according to the check result; Running the first error correction code operation or the second error correction code operation on the message bit according to the indicator to generate a plurality of updated message bits and a plurality of updated parity check bits; and A write operation for writing the updated message bit, the updated parity check bit, and the indicator into the memory device is performed based on the address information. The data access method described in item 3 of the scope of patent application, wherein the step of checking the number of error bits of the codeword during the pre-reading and the writing verification reading process to obtain the checking result include: Performing the pre-reading process based on the address information to obtain a read codeword; and The write verification read process is performed on the read codeword to obtain the check result. The data access method described in item 3 of the scope of patent application, wherein the execution is configured to write the updated message bit, the updated parity check bit, and the indicator in the address information based on the address information. The steps of the writing operation of the memory device include: The updated message bit, the updated parity check bit, and the indicator are written into the memory device according to the number of error bits. The data access method described in item 3 of the scope of patent application, wherein the first logic level is logic level 1 and the second logic level is logic level 0, and the data access method further includes: If the number of error bits is equal to 0, set the indicator to the first logic level; If the number of error bits is greater than 0, set the indicator to the second logic level, wherein the first logic level is complementary to the second logic level; When the indicator is the first logic level, perform a write verification read operation after the write operation based on the address information; If the number of checked error bits is greater than 0, update the indicator to the second logic level; and Enable and execute the second error correction code operation on the updated message bit. The data access method described in the first item of the patent application, wherein the first error correction code operation is based on 4 sets of Hamming (12, 8) codes, and the second error correction code operation is based on 1 set of BCH (50, 32) code operation. For example, the data access method described in item 3 of the scope of patent application includes: Providing a first write pulse to write the indicator to the memory device during the write operation; and Providing a second write pulse to write the updated message bit to the memory device during the write operation, Wherein the first write pulse is different from the second write pulse. A memory device includes: Memory cell array; and The controller, coupled to the memory cell array, is configured to: Performing a read operation on the memory device based on the address information to obtain a codeword and an indicator, wherein the indicator corresponds to the codeword; and Causing the first error correction code operation or the second error correction code operation to run on the codeword for generating error correction data, Wherein, the first error correction code operation corrects fewer bits than the second error correction code operation. The memory device according to claim 9, wherein the controller sets the indicator according to the number of error bits of the codeword. The memory device according to claim 10, wherein the codeword includes a plurality of message bits and a plurality of corresponding parity check bits, and the controller is further configured to: Receiving a data write command based on the address information; Checking the number of error bits of the codeword during the pre-reading and writing verification read process to obtain a check result; Set the indicator according to the check result; Running the first error correction code operation or the second error correction code operation on the message bit according to the indicator to generate a plurality of updated message bits and a plurality of updated parity check bits; and Perform a write operation for writing the updated message bit, the updated parity check bit, and the indicator into the memory cell array based on the address information. In the memory device described in item 9 of the scope of patent application, the controller is further configured to: Performing the pre-reading process based on the address information to obtain the codeword; and The write verification read process is performed on the codeword to obtain the check result. The memory device according to claim 11, wherein the controller writes the updated message bit, the updated parity check bit, and the indicator according to the number of error bits The memory cell array. The memory device described in item 11 of the scope of patent application, wherein if the number of error bits is equal to 0, the controller sets the indicator to the first logic level; if the number of error bits is Greater than 0, the controller sets the indicator to a second logic level, wherein the first logic level is complementary to the second logic level, The first logic level is logic level 1 and the second logic level is logic level 0, and the controller is further configured to: When the indicator is the first logic level, perform a write verification read operation after the write operation based on the address information; If the number of checked error bits is greater than 0, update the indicator to the second logic level; and Enable and execute the second error correction code operation on the updated message bit. The memory device according to the ninth patent application, wherein the first error correction code operation is based on 4 sets of Hamming (12, 8) codes, and the second error correction code operation is based on 1 set of BCH ( 50, 32) code operation. In the memory device described in item 9 of the scope of patent application, the controller is further configured to: Providing a first write pulse to write the indicator to the memory device during the write operation; and Providing a second write pulse to write the updated message bit to the memory device during the write operation, Wherein the first write pulse is different from the second write pulse.

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