CN114333968A

CN114333968A - Memory control method, memory controller and electronic device

Info

Publication number: CN114333968A
Application number: CN202111642206.0A
Authority: CN
Inventors: 王晓耕
Original assignee: Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2022-04-12

Abstract

Provided are a memory control method, a memory controller and an electronic device. The method includes receiving a sparse write request, the sparse write request indicating target data to be written to memory and a target address segment to be written to memory; reading first data and a first check code corresponding to the first data from a first address field of a memory, wherein the first address field covers a target address field; verifying the first data by using the first verification code, and in response to the verification passing, modifying the first data by using the target data according to the corresponding relation between the target address field and the first address field to obtain second data; and verifying the second data to obtain a second check code, writing the second data into the first address segment of the memory and storing the second check code. Original data in the memory is modified by using target data to be written into the memory, single byte access is avoided, check bits required to be set by the memory supporting the sparse write request are reduced, and cost is reduced.

Description

Memory control method, memory controller and electronic device

Technical Field

The embodiment of the disclosure relates to a control method of a memory, a memory controller and an electronic device.

Background

Single and multiple bit flips, or fixed "0" or "1" failures, may occur in memories, such as Static Random-Access memories (SRAMs). The reasons for this phenomenon are many, and typically include single event effect, i.e. single energetic particle causes flip-flop flip.

For such failures, Error Correction Code (ECC) is usually used to implement Error correction and protection for the memory. Current ECC error and detection functions require the use of redundant error correction codes. For a conventional write request (which may also be called a write command, a write instruction, or a write operation), writing 8-bit data requires a 5-bit check code, writing 16-bit data requires a 6-bit check code, writing 32-bit data requires a 7-bit check code, and writing 64-bit data requires an 8-bit check code. However, for some special write requests, such as sparse write requests (which may also be referred to as sub-word write requests), which need to support single byte access, a 5-bit check code is needed to write 8-bit data, a 10-bit check code is needed to write 16-bit data, a 20-bit check code is needed to write 32-bit data, and a 40-bit check code is needed to write 64-bit data. This corresponds to a direct increase in the area of the memory by 62%, which greatly increases the cost.

Disclosure of Invention

At least one embodiment of the present disclosure provides a memory control method, a memory controller, and an electronic device, which solve the technical problem in the prior art that a memory that needs to support sparse writing needs to set a large number of check bits, so that the cost is high.

At least one embodiment of the present disclosure provides a method of controlling a memory, including: receiving a sparse write request, wherein the sparse write request indicates target data to be written to memory and a target address segment to be written to memory; reading first data and a first check code corresponding to the first data from a first address field of a memory, wherein the first address field covers a target address field, and the length of the first address field is greater than or equal to that of the target address field; verifying the first data by using the first verification code, and in response to the verification passing, modifying the first data by using the target data according to the corresponding relation between the target address field and the first address field to obtain second data; and verifying the second data to obtain a second check code, writing the second data into the first address segment of the memory and storing the second check code.

For example, in one embodiment of the present disclosure, a method is provided in which the target address segment corresponds to an address segment of at least one byte in length in the first address segment.

For example, in a method provided by an embodiment of the present disclosure, modifying first data using target data to obtain second data includes: and replacing data of the same length as the target data in the first data with the target data.

For example, in a method provided by an embodiment of the present disclosure, replacing data of the first data with the same length as the target data by the target data, where the sparse write request further indicates an identifier indicating a location of the target data in the target address field, includes: and replacing the data corresponding to the position in the first data with the target data according to the position.

For example, in a method provided in an embodiment of the present disclosure, after the first data is checked by using the first check code, the method further includes: and outputting error information in response to the verification failing.

For example, in a method provided by an embodiment of the present disclosure, before receiving a sparse write request, the method further includes: detecting the power-on condition of a memory; the memory is initialized in response to the memory being powered up.

For example, in a method provided by an embodiment of the present disclosure, initializing a memory includes: writing third data into a second address field in the memory, and generating and storing a check code corresponding to the third data; the second address field is all addresses of the memory or addresses used for storing check codes in the memory.

At least one embodiment of the present disclosure provides a memory controller, including a receiving module, a checking module, and a data modifying module, wherein the receiving module is configured to receive a sparse write request, wherein the sparse write request indicates target data to be written to a memory and a target address segment to be written to the memory; the checking module is configured to read first data and a first checking code corresponding to the first data from a first address segment of the memory, and check the first data by using the first checking code, wherein the first address segment covers a target address segment, and the length of the first address segment is greater than or equal to that of the target address segment; the data modification module is configured to respond to the verification passing and modify the first data by using the target data according to the corresponding relation between the target address field and the first address field to obtain second data; and the verification module is further configured to verify the second data to obtain a second verification code, write the second data to the first address segment of the memory and save the second verification code.

For example, in a memory controller provided by an embodiment of the present disclosure, the target address segment corresponds to an address segment of at least one byte in length in the first address segment.

For example, in a memory controller provided by an embodiment of the present disclosure, the data modification module is configured to replace data of the same length as the target data in the first data with the target data.

For example, in the memory controller provided by an embodiment of the present disclosure, the sparse write request further indicates an identifier indicating a location of the target data in the target address field, and the data modification module is configured to replace, by the location, data in the first data corresponding to the location with the target data.

For example, in a memory controller provided in an embodiment of the present disclosure, the memory controller further includes: an error output module configured to output an error message in response to the verification failing.

For example, in a memory controller provided in an embodiment of the present disclosure, the memory controller further includes: a detection module configured to detect a power-up condition of the memory; and an initialization module configured to initialize the memory in response to the memory being powered on.

For example, in a memory controller provided by an embodiment of the present disclosure, the initialization module is configured to perform data flash on a second address in the memory, so that the second address stores the same data; the second address is the whole address of the memory or the address used for storing the check code in the memory.

At least one embodiment of the present disclosure provides an electronic device including a memory controller and a memory as in any one of the above embodiments.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it should be apparent that the drawings described below only relate to some embodiments of the present disclosure and are not limiting on the present disclosure.

FIG. 1A is a schematic circuit diagram of an SRAM;

FIG. 1B is a schematic diagram of an equivalent memory array of the SRAM shown in FIG. 1A;

fig. 2A is a flowchart of a method for controlling a memory according to at least one embodiment of the disclosure;

fig. 2B is a schematic diagram of a memory controller according to at least one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of another memory controller provided in at least one embodiment of the present disclosure;

fig. 4 is a schematic view of an electronic device according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

At least one embodiment of the present disclosure provides a method of controlling a memory, including receiving a sparse write request indicating target data to be written to the memory and a target address segment to be written to the memory. Reading first data and a first check code corresponding to the first data from a first address field of the memory, wherein the first address field covers the target address field, and the length of the first address field is greater than or equal to that of the target address field. And verifying the first data by using the first verification code, and modifying the first data by using the target data according to the corresponding relation between the target address field and the first address field in response to the verification passing to obtain second data. And verifying the second data to obtain a second check code, writing the second data into the first address segment of the memory and storing the second check code.

At least one embodiment of the present disclosure provides a memory controller including a receiving module, a verifying module, and a data modifying module. The receiving module is configured to receive a sparse write request indicating target data to be written to memory and a target address segment to be written to memory. The checking module is configured to read first data and a first checking code corresponding to the first data from a first address field of the memory, check the first data by using the first checking code, wherein the first address field covers a target address field, and the length of the first address field is greater than or equal to that of the target address field. And the data modification module is configured to respond to the verification passing and modify the first data by using the target data according to the corresponding relation between the target address field and the first address field to obtain second data. The check module is further configured to check the second data for a second check code, write the second data to the first address segment of the memory and save the second check code.

At least one embodiment of the present disclosure provides an electronic device including a memory controller and a memory as in the above embodiments.

At least one embodiment of the disclosure provides a control method of a memory, a memory controller and an electronic device. The method modifies the original data in the memory by using the target data to be written into the memory, avoids single byte access, does not need check codes for the single byte access, and realizes the reduction of check bits required to be set by the memory supporting the sparse write request and the cost reduction.

FIG. 1A is a schematic circuit diagram of a Static Random Access Memory (SRAM), and FIG. 1B is a schematic memory array diagram of the SRAM equivalent to FIG. 1A.

As shown in FIG. 1A, the SRAM circuit mainly includes a row address decoding, a column address decoding, a bit line selection, a column multiplexer, and a memory array. The width of read-write data of the static random access memory is m bits, the width of read-write address is S bits, the width of column address is k bits, and the width of row address is S-k bits. After decoding the row address, selecting a row in the memory array by a word line, wherein one row in the memory array comprises 2^kGroup m bits of data. Decoding the column address to obtain a column strobe address, and selecting a row 2 selected by the word line through the column multiplexer^kA set of m-bit data of the set of m-bit data is read or written.

As shown in fig. 1B, the sram may be equivalent to a two-dimensional array of n rows and m bits per row, for example, n ═ 2^S. Each block in fig. 1B is a memory cell, i.e., a bit, in the sram. m bits represent the storage bit width, i.e., the data width processed during a single read-write operation.

For various reasons, the sram may have data errors, i.e., data read from the same address is not equal to data written previously. The errors of the sram are mainly classified into two types:

the first type is hard errors, i.e. the circuits of the memory array of the internal part of the sram are permanently damaged, resulting in irreversible errors of this part of the data. Such errors are mainly caused by defects In the chip manufacturing process and circuit aging, an MBIST (Memory built-In-Self Test) circuit can be used to detect a Memory region In which an error occurs, and the Memory region In which an error occurs needs to be avoided In the chip using process.

The second type is soft errors, which are not permanent and disappear after writing new data to the same address. The main causes of soft errors include two: the penetration of radioactive particles causes the inversion of the memory cell of the static random access memory, and the dynamic voltage noise causes the inversion of the memory cell when reading and writing data. As transistor sizes shrink, the operating voltages of the sram become lower and lower, and the distances between adjacent memory cells in the sram become closer, which results in the soft errors of the sram becoming more common. Since the soft error is a dynamic error, which may occur in data reading and writing at any time and any position when the chip normally operates, and cannot be detected and avoided in advance like a hard error, the soft error must be dynamically processed. Detection of soft errors typically occurs at the time of data read. When a soft error in the static random access memory is detected, firstly, whether the data can be directly corrected is judged, and if the data can be corrected, the corrected data is directly returned. For example, when 1-bit error occurs, a SECDED (single-error correction and double-error detection) circuit may be used to correct the error.

Similar to a conventional write request/access, a sparse write request for the static random access memory includes a target address field of data to be written and target data to be written. The target address segment in the sparse write request involved in the embodiments of the present disclosure may be the same length as a conventional write request, e.g., 16 bits, 32 bits, or 64 bits, as opposed to the target data to be written being smaller in length than the target address segment, e.g., 8 bits, 16 bits, or 32 bits, respectively, i.e., the target data cannot fill up the target address segment, which may be understood to be sparse with respect to the target address segment.

Fig. 2A illustrates a flowchart of a method for controlling a memory according to at least one embodiment of the present disclosure. For example, the memory may be a static random access memory as shown in fig. 1A and 1B, but embodiments of the present disclosure are not limited thereto.

As shown in fig. 2A, the memory control method includes the steps of:

s101, receiving a sparse write request, wherein the sparse write request indicates target data to be written into a memory and a target address field to be written into the memory.

S102, reading first data and a first check code corresponding to the first data from a first address segment of a memory, wherein the first address segment covers a target address segment, and the length of the first address segment is greater than or equal to that of the target address segment.

S103, the first data is verified by using the first verification code, and in response to the verification passing, the first data is modified by using the target data according to the corresponding relation between the target address field and the first address field to obtain second data.

S104, checking the second data to obtain a second check code, writing the second data into the first address segment of the memory and saving the second check code.

First, step S101 is performed. The sparse write request may carry a target address segment, and a length of a storage space corresponding to the target address segment is greater than or equal to a length of the target data. For example, the target data is 2 bytes in length, and the target address field is 4 bytes in length. As another example, the target data is 4 bytes in length, and the target address field is also 4 bytes in length.

The sparse write request may also carry an identifier indicating the target data, which indicates which byte or bytes of data input to the data lines of memory are the target data. For example, the total length of the input data is 8 bytes, the identifier is "11000100", the target data is the 1 st, 2 nd and 6 th bytes of the input data, and the remaining 5 bytes of the input data are not written to the memory.

Before executing step S101, it may also be determined whether the received write request is a sparse write request. For example, the sparse write request includes an indication bit, and when the indication bit takes a value of "1", the write request is a sparse write request. For another example, while receiving the write request, an enable signal is received that indicates that the currently received write request is a sparse write request.

Next, step S102 is executed. During execution, the first address segment is obtained according to the target address segment. For example, the target address segment is the first address segment, or the target address segment corresponds to an address segment of at least one byte in length in the first address segment. When the length of the target address segment is less than the length of the first address segment, the first address segment may be obtained based on the target address segment and the identifier.

After the first address segment is acquired, the first data and the corresponding first check code are read from the memory.

After step S102 is executed, step S103 is executed.

The first data is checked by using the first check code obtained in step S102, for example, the check at this time is, for example, ECC encoding, for example, an RS (Reed-Solomon) algorithm or a hamming code algorithm is adopted, and the embodiment of the present disclosure has no limitation on the check algorithm. The check in this embodiment may be considered as decoding the first data by using the first check code, and the decoding or encoding below does not affect the information represented by the first data.

When the check passes, the corresponding relation between the target address field and the first address field is used to determine how to modify the first data by using the target data. For example, if the target address segment is 3 bytes in the first address segment, the 3 bytes in the first data are modified by the target data, and the position of the modified 3 bytes in the first data corresponds to the position of the target address segment in the first address segment.

Alternatively, the target data may be used to replace data of the same length as the target data in the first data. For example, the target data is "01010001", the first data is "0100010010010011 ", obtaining the second data as"0101000110010011”。

When the length of the target data is less than the length of the target address segment, i.e., the target address segment corresponds to the length of a full word write, and the length of the target data is the length of a sparse write, the sparse write request also indicates an identifier indicating the location of the target data in the target address segment. The identifier indicates a location in the destination address field where the destination data is to be written. For example, the identifier is "1001" indicating that the 1 st byte and the 4 th byte are to be written with the target data.

The data of the first data at the position corresponding to the position may be replaced with the target data according to the position. In this embodiment, the target address field is the first address field, for example, the identifier is "111100", and the first 4 bytes in the first data are replaced by the target data without changing the last 2 bytes.

After the execution of step S103 is completed, step S104 is executed.

In this embodiment, data needs to be checked before being written into the memory, the check at this time is, for example, ECC encoding, for example, using RS algorithm or hamming code algorithm, and the same check algorithm is used for writing and reading. The length of the second data is the same as that of the first data, so that single-byte access does not exist for the memory, the length of the check code required by the second data is the same as that of a conventional write request, and the length of the check code can be greatly shortened compared with that of a sparse write request.

Optionally, after step S103 is executed, if the first data is not verified by using the first verification code, that is, the first data is read with an error, the error information is output in response to the verification failing.

The error information includes an error type and an address where the error occurred. The error type includes, for example, a single bit error or a double bit error. The address at which the error occurred is the first address segment. The error information is output to, for example, a host, a CPU, a processor, or the like.

Further optionally, before performing step S101, the control method further includes detecting a power-on condition of the memory. The memory is initialized in response to the memory being powered up.

When the memory is powered on, if the memory is not initialized, the memory space in the memory is equivalent to the random numerical value with irregularity. This may result in a mismatch between the location in memory used to store the data and the location used to store the check code. The random values make the memory unable to be used for the sparse write operation, so that when the memory is detected to be powered on, the memory is initialized, data stored in a storage space of the memory are the same or accord with a preset rule, and the memory can be applied to sparse write.

Optionally, initializing the memory comprises: third data is written to the second address field in the memory, and a check code corresponding to the third data is generated and stored. The second address field is all addresses of the memory or addresses used for storing check codes in the memory.

In this embodiment, initializing the memory may select to write the same data to all address segments of the memory or to write the same data only to the address in the memory for storing the check code. The check code of the data in the memory may be stored with the data or the data and the check code may be stored separately.

For example, the third data is "0" or "1", and all address segments in the memory are written into "0" or "1", but it should be noted that "0" or "1" is encoded "0" or "1", i.e. it needs to be checked with a check code after reading.

Fig. 2B illustrates a schematic diagram of a memory controller provided in accordance with at least one embodiment of the present disclosure.

In FIG. 2B, the memory controller 200 includes a receive module 210, a check module 220, and a data modification module 230. The receiving module 210 is coupled to the verifying module 220 and the data modifying module 230, and the verifying module 220 is coupled to the data modifying module 230.

The receiving module 210 receives a sparse write request. The sparse write request indicates target data to be written to memory and a target address segment to be written to memory.

The checking module 220 reads the first data and a first check code corresponding to the first data from a first address segment of the memory 240, and checks the first data by using the first check code, wherein the first address segment covers the target address segment, and the length of the first address segment is greater than or equal to the length of the target address segment.

The data modification module 230 modifies the first data with the target data to obtain second data according to the corresponding relationship between the target address field and the first address field in response to the verification passing.

The check module 220 also checks the second data to obtain a second check code, writes the second data to the first address segment of the memory 240, and stores the second check code.

The memory controller modifies original data in the memory by using target data to be written into the memory, avoids single-byte access, does not need check codes for the single-byte access, reduces check bits required to be set by the memory supporting sparse write requests, and reduces cost.

The memory controller 200 may execute the methods described in the above method embodiments, and specific execution manners may be referred to the above description, which is not expanded herein.

Optionally, the target address segment corresponds to an address segment of at least one byte in length in the first address segment.

Optionally, the data modification module is configured to replace data of the same length as the target data in the first data with the target data.

Optionally, the sparse write request further indicates an identifier indicating a location of the target data in the target address field, and the data modification module is configured to replace data of the first data at a location corresponding to the location with the target data by location.

Optionally, the memory controller further comprises an error output module configured to output an error message in response to the verification failing.

Optionally, the memory controller further comprises a detection module and an initialization module. The detection module is configured to detect a power-up condition of the memory. The initialization module is configured to initialize the memory in response to the memory being powered on.

Optionally, the initialization module is configured to perform a data flash on a second address in the memory, so that the second address stores the same data. The second address is the whole address of the memory or the address used for storing the check code in the memory.

FIG. 3 is a schematic diagram of another memory controller according to at least one embodiment of the present disclosure.

As shown in FIG. 3, the memory controller 300 includes a state machine module 310, an ECC encoder 320, an ECC decoder 330, and multiplexers 340-360. For example, compared to the schematic of fig. 2B, the state machine module 310 may correspond to the data modification module 230 in the memory controller 200, and the ECC encoder 320 and the ECC decoder 330 correspond to the check module 220 in the memory controller 200. The receiving module 210 may correspond to an interface (not shown) through which the memory controller 300 interacts with a host.

The state machine module 310 and the ECC encoder 320 are connected to the memory 370 through the multiplexer 340. The memory 370 and the ECC decoder 330 output the read data through the multiplexer 350. The externally input write data, the state machine module 310 and the ECC decoder 330 are connected to the ECC encoder 320 through the multiplexer 360.

Memory 370 is a memory with ECC check bits. For example, 8-bit data requires 5-bit check bits, 16-bit data requires 6-bit check bits, 32-bit data requires 7-bit check bits, and 64-bit data requires 8-bit check bits.

ECC encoder 320 encodes the data written to memory 370 using conventional encoding. Such as Hsiao codes, hamming codes, etc. For example, 32-bit data uses a (39,32) Hsiao code, and 64-bit data uses a (72,64) Hsiao code. The coding mode supports single-bit error correction and double-bit error detection.

When reading data, the ECC decoder 330 decodes the read data in a decoding manner corresponding to the encoder 320, to obtain original data.

For example, the state machine module 310 may include a sparse write state machine and a self-initializing state machine. For example, in at least one embodiment, the sparse write state machine and the self-initialization state machine are comprised of state registers and combinational logic circuitry. The state machine module 310 includes a plurality of ports for transmitting init i/f, err reporting i/f, ram _ en, ram _ wr, ram _ addr, ram _ byte _ en, and ram _ busy, respectively.

init i/f indicates the initialization to the state machine module 310 by the host and reports the completion of the initialization to the host by the state machine module 310. The err reporting i/f is that the state machine module 310 reports error information to the host. The error information includes an error type and an address. ram _ en, ram _ wr are the hosts input write enables to the state machine module 310. ram _ addr, ram _ byte _ en are the address of the write request input by the host to the state machine module 310 and the enable signal that the write request is a sparse write request. ram busy is reported to the host by the state machine module 310.

The multiplexer 340 receives data from the state machine module 310 and the ECC encoder 320 to be written to the memory 370.

The multiplexer 350 receives the read data from the ECC decoder 330 or the ECC data intercepted by the memory 370.

The multiplexer 360 receives init _ wrdata (data to be written to the memory at initialization) from the state module 310, ram _ wrdata (write data) externally input, and spare _ wrdata (data to be written to the memory for a sparse write request) from the ECC decoder 330.

The memory controller 300 utilizes a state machine and an ECC codec to perform the methods in the method embodiments described above.

For example, the sparse write state machine may implement the sparse write request in the above method, and the self-initialization state machine may implement the initialization of the memory. The self-initialization state machine is a built-in state so that initialization is accomplished without the need for a host or CPU to send a large number of write requests to the memory.

Take sparse write state machine as an example. During a first cycle, the host issues a sparse write request to memory 370, during which first cycle full word read access is issued to memory 370, and during which first cycle sparse write request information is registered.

During the second cycle, memory 370 provides read data, which contains check bits, and the original full word data, e.g., the first data, is decoded by ECC decoder 330. The sparse write state machine rewrites a part of bytes in the full-word data in the second cycle, to obtain, for example, second data. The written new data is then encoded (check bits added) by the ECC encoder 320 and written back to the memory 370. In the second cycle, decoding, rewriting and encoding of read data are all combinational logic, and thus can be completed in one cycle.

One way to implement data overwriting is as follows:

the byte is a byte-wise byte enabling bit in the secondary word access information, the data _ value1 is target data to be written in the sparse write request information, and the data _ value2 is original full word data obtained by reading and accessing the memory in the last period.

For the self-initialization state machine, self-initialization writes a "0" value to the specified address field and then writes to memory 370 via ECC encoder 320. The self-initializing state machine has three states, IDLE, START _ INIT, DONE. The default state machine is in an IDLE state, when the INIT _ START _ i signal is high, the state machine is switched to a START _ INIT state, initialization writing is carried out from the INIT _ START _ addr, the memory address +1 is stored every period until the INIT _ end _ addr is switched to a DONE state, and the INIT _ START _ i is pulled down and then returns to the IDLE state.

Wherein the address self-increment logic at START _ INIT is implemented as follows:

fig. 4 is a schematic diagram of an electronic device according to at least one embodiment of the present disclosure.

In fig. 4, an electronic device 400 includes a memory controller 410 and a memory 420. The memory 420 is coupled with the memory controller 410. The memory controller 410 is, for example, the memory controller 200 or the memory controller 300. The memory 420 may be, for example, an SRAM, a flash memory, etc., and the embodiment of the disclosure is not limited thereto.

The electronic device 400 may be used in a computer system, for example, as a memory or a hard disk, and thus may be accessed by a central processing unit, a Direct Memory Access (DMA), and the like through a bus, such as a PCI, PCIE, and the like type bus.

The memory controller 410 may execute the methods described in the above method embodiments, and the specific execution manner may refer to the above description, which is not described herein again.

All or portions of the various elements described in this disclosure may be implemented in suitable hardware, software, or hardware in combination with software, e.g., in dedicated circuitry, firmware, software, or any combination thereof. For example, certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device.

The processes described above may also be implemented as computer software programs in accordance with embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program containing program code for performing the methods of the above-described processes.

The method flow diagrams and device block diagrams referred to in this disclosure are only exemplary examples, and are not intended to require or imply that the connections, arrangements, or steps must be made in the manner illustrated in the flow diagrams and block diagrams. These devices, apparatuses may be connected, arranged in any manner as long as the desired purpose is achieved, as will be appreciated by those skilled in the art.

The scope of the present disclosure is not to be limited by the specific embodiments of the present disclosure, but is to be determined by the scope of the appended claims. The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs. Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

Claims

1. A method of controlling a memory, comprising:

receiving a sparse write request, wherein the sparse write request indicates target data to be written to memory and a target address segment to be written to the memory;

reading first data and a first check code corresponding to the first data from a first address segment of the memory, wherein the first address segment covers the target address segment, and the length of the first address segment is greater than or equal to that of the target address segment;

checking the first data by using the first check code, and in response to the passing of the checking, modifying the first data by using the target data according to the corresponding relation between the target address field and the first address field to obtain second data; and

and checking the second data to obtain a second check code, writing the second data into the first address section of the memory and saving the second check code.

2. The method of claim 1, wherein the target address segment corresponds to an address segment of at least one byte in length in the first address segment.

3. The method of claim 1 or 2, wherein said modifying said first data using said target data results in second data, comprising:

and replacing data with the same length as the target data in the first data by using the target data.

4. The method of claim 3, wherein the sparse write request further indicates an identifier indicating a location of the target data in the target address segment, the replacing, with the target data, data of the first data that is the same length as the target data, comprising:

and replacing the data in the first data, which is at the position corresponding to the position, by the target data according to the position.

5. The method of claim 1, wherein after verifying the first data using the first verification code, the method further comprises:

outputting an error message in response to the check failing.

6. The method of claim 1, wherein prior to said receiving a sparse write request, the method further comprises:

detecting a power-on condition of the memory;

initializing the memory in response to the memory being powered up.

7. The method of claim 6, wherein the initializing the memory comprises:

writing third data into a second address field in the memory, and generating and storing a check code corresponding to the third data;

the second address field is all addresses of the memory or addresses used for storing check codes in the memory.

8. A memory controller includes a receiving module, a verifying module, and a data modifying module, wherein,

the receiving module is configured to receive a sparse write request, wherein the sparse write request indicates target data to be written to a memory and a target address segment to be written to the memory;

the checking module is configured to read first data and a first check code corresponding to the first data from a first address segment of the memory, and check the first data by using the first check code, wherein the first address segment covers the target address segment, and the length of the first address segment is greater than or equal to that of the target address segment;

the data modification module is configured to respond to the verification passing, modify the first data by using the target data according to the corresponding relation between the target address field and the first address field, and obtain second data; and

the check module is further configured to check the second data for a second check code, write the second data to the first address segment of the memory and save the second check code.

9. The memory controller of claim 8, wherein the target address segment corresponds to an address segment of at least one byte in length in the first address segment.

10. The memory controller of claim 8 or 9, wherein the data modification module is configured to replace data of the first data that is the same length as the target data with the target data.

11. The memory controller of claim 10, wherein the sparse write request further indicates an identifier indicating a location of the target data in the target address segment, the data modification module configured to replace data of the first data at a location corresponding to the location with the target data by the location.

12. The memory controller of claim 8, wherein the memory controller further comprises:

an error output module configured to output an error message in response to the check failing.

13. The memory controller of claim 8, wherein the memory controller further comprises:

a detection module configured to detect a power-up condition of the memory; and

an initialization module configured to initialize the memory in response to the memory being powered up.

14. The memory controller of claim 13, wherein the initialization module is configured to data-flash a second address in the memory such that the second address stores the same data;

the second address is all addresses of the memory or addresses used for storing check codes in the memory.

15. An electronic device, comprising:

the memory controller of any of claims 8-14; and

the memory.