JPH08166891A - Fault tolerant computer system - Google Patents

Abstract

PURPOSE: To realize a system where an error correction becomes possible without applying overhead and the lowering of processing speed is not invited. CONSTITUTION: A pilot processor 220 is operated without an error correction proceeding a master processor 210. Based on the signal from the preceding pilot processor 220, an error correction circuit is made to perform a preceding operation. The data for which an error correction is already performed is supplied to the master processor 210.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a detection and correction system and a fault tolerant computer system, and more particularly to a detection and correction system and a fault tolerant computer system suitable for high speed operation.

[0002]

2. Description of the Related Art Some bits of data stored in a memory (storage device) are inverted by being affected by electrical noise, radiation, cosmic rays, etc., resulting in erroneous data and soft errors. A phenomenon called single event upset may occur. When this phenomenon occurs, the normal operation of the computer system is hindered and reliability is reduced. This phenomenon tends to occur particularly frequently in special environments such as space. In addition, the effect of this phenomenon cannot be ignored in systems that require high reliability even on the ground.

In order to deal with an error in data in a memory, a conventional method has been to add a parity bit to the data to detect the error, or an error correction code having a higher degree of redundancy than the parity to detect and correct the error. The method of doing is widely used.

[0004]

In the prior art, sufficient consideration was given to reliability improvement, but not sufficient consideration to speeding up the operation.

For example, when writing data in the memory, it is necessary to generate a parity bit for error detection and correction and an error correction code and write it in the memory together with the data. Therefore, as compared with a normal computer system that does not have a parity bit and an error correction code, an extra time (overhead) is required for the time for generating these codes, and the operation speed is reduced.

Further, when reading data from the memory, the parity bit and the error correction code are read out from the memory together with the data, and the presence or absence of an error is checked by collating with the data. In the case of the error correction code, when an error occurs, Further error corrections have to be made. Therefore the parity bit,
Compared with an ordinary computer system that does not have an error correction code, an extra time (overhead) is required only for the time of collating the data with the parity bit and the error correction code, and the error correction, and the operation speed decreases.

An object of the present invention is to eliminate a decrease in operation speed due to adding a parity bit and an error correction code,
An object of the present invention is to provide a computer system that can operate at a speed comparable to that of a normal computer system that does not have a parity bit or an error correction code.

[0008]

In order to solve the problems of the prior art, the present invention takes the following means.

First, a processor (pilot processor) that accesses the memory without error detection and correction and a processor (master processor) that accesses the memory with error detection and correction are prepared, and the same operation (instruction execution) is performed on both.
Let Then, the pilot processor that does not require the overhead for error detection and correction can operate in advance of the master processor. That is, by monitoring the operation of the pilot processor that is operating in advance, it is possible to predict the operation of the master processor in advance. Focusing on this point, an error detection / correction circuit for the master processor to access the memory with error detection / correction is operated in advance based on the signal from the pilot processor.

[0010]

According to the present invention, since the pilot processor does not require the overhead for error detection and correction, it can operate at high speed. In addition, the error detection and correction circuit for the master processor to access the memory with error detection and correction operates in advance based on the operation of the pilot processor. It can operate at virtually the same speed as the pilot processor, but with error detection and correction. Furthermore, by comparing and checking the outputs of the two processors, the pilot processor and the master processor, the processor itself can be made self-checking.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

A read access operation according to the present invention is conceptually shown in FIG. A pilot processor (MPU (pilot)) 220 outputs an address 221 and a control signal 222 as the instruction is executed. The memory (MEM) 310 outputs required data 223 based on the address 221 and the control signal 222. Pilot processor 22
0 fetches the data 223 and moves to the execution of the next instruction.
On the other hand, the error correction circuit (ECC CKT) 230 performs error detection / correction operation and passes the error-corrected data 213 to the master processor (MPU (master)) 210. The master processor 210 fetches the data 213 and moves on to execute the next instruction. Since the pilot processor 220 can complete the execution of instructions in a shorter time than the master processor 210 because there is no error correction, it is possible to always advance the execution of instructions. In addition, the memory 310,
Since the error correction circuit 230 also operates in advance based on the signal from the preceding pilot processor 220, the overhead associated with the operation of the error correction circuit 230 is invisible to the master processor 210.

The operation during write access according to the present invention is conceptually shown in FIG. Pilot processor 220
The error correction circuit 230 generates an ECC (error correction code) corresponding to the data 223 output from
21 and write to the memory 310 according to the control signal 222. At the time of write access, as long as both the master processor 210 and the pilot processor 220 have passed the data 223 to the error correction circuit 230, the next instruction can be executed without waiting for the completion of writing to the memory 310.

3 and 4 show the address 21 output from the master processor 210 and pilot processor 220.
1, 221, control signals 212, 222, data 213, 2
This is an example in which 23 pieces are compared and checked. At the time of read access, as shown in FIG. 3, addresses 211, 221,
By comparing the control signals 212 and 222 with each other, the malfunction of the master processor 210 and the pilot processor 220 can be detected. At the time of write access, as shown in FIG.
In addition to 2, 222, by comparing the data 213, 223, the malfunction of the master processor 210 and pilot processor 220 can be detected. Furthermore, after the data 213 and 223 match each other, the memory 3
By writing the data in 10, it is possible to prevent the erroneous data from being written in the memory 310 due to the malfunction of the master processor 210 and the pilot processor 220.

FIG. 5 schematically shows the operation of an error correction circuit according to the prior art. On the other hand, FIG. 6 schematically shows the operation of the error correction circuit according to the present invention. As shown in FIG. 5, in the method according to the conventional technique, an overhead for error detection / correction is applied every time an instruction for accessing a memory is executed, which causes deterioration in processing performance. On the other hand, the method according to the present invention can eliminate the overhead as shown in FIG. The operation of the method according to the present invention will be described below. The pilot processor 220 and the master processor 210 simultaneously reset the first instruction inst.1 after reset.
Start executing. The master processor 210 delays the end of execution of inst.1 by the amount of overhead due to error correction. When the master processor 210 starts executing the instruction inst.2, the pilot processor 220 has already executed the instruction.
Since the execution of inst.2 has been completed and the error correction circuit is also operating in advance according to the pilot processor 220, the master processor 210 can execute the instruction without overhead due to error correction.
You can finish the execution of inst.2. As described above, the master processor 210 can execute instructions one after another without the overhead of error correction based on the operation of the pilot processor 220 which precedes.

FIG. 6 shows the pilot processor 220.
And the master processor 210 share the memory and the error correction circuit, the memory contention does not occur, and is shown on the assumption of an ideal case. Actually, depending on the preceding and succeeding instructions, the pilot processor 220 and the master processor 210 simultaneously execute different instructions occupying the memory and the error correction circuit, so that competition between the memory and the error correction circuit occurs as shown in FIG. In the figure, NG indicates that competition has occurred, and OK indicates that competition has not occurred. Although omitted in the figure, it goes without saying that no conflict occurs before and after an instruction that does not access the external memory (for example, an arithmetic instruction, a register access, an instruction that accesses only the internal cache memory, etc.). If there is a conflict, pilot processor 220 may execute the next instruction after the conflict is resolved. FIG. 8 shows an operation state when a conflict occurs between the instructions inst.3 and inst.4.

According to the embodiment described above, since the master processor 210 can be operated at the same speed with error correction subsequent to the pilot processor 220 that operates at high speed without error correction, both processing performance and reliability are high. A computer system can be realized.

FIG. 9 shows an embodiment of a circuit configuration when the master processor 210 and the pilot processor 220 share the memory (MEM) 310. The address 221 from the pilot processor 220 is an error correction circuit (EC
Address register (ADD R in C CKT) 110
EG) 116 to the address 211 'and the memory 31
Connecting to 0 is a characteristic different from the conventional method.

The operations of (1) read access, (2) full-write access, and (3) partial-write access of this embodiment will be described below.

(1) Read access At the time of read access, the data 2 is read from the memory 310 based on the address 221 from the pilot processor 220.
13 'and the error correction code 213 "are output. Of these, the data 213' is the pilot processor 22.
0 is supplied as data 223. Therefore, the pilot processor 220 ends the read access at this point and moves on to the execution of the next instruction.

Data 21 read from the memory 310
3 ′ and the error correction code 213 ″, the error correction code decoder (ECC DEC) 103 determines whether or not there is an error.
The syndrome (signal indicating the error bit position) 108 is determined. If there is no error, the read data 212 '
Are stored in the data register 101 as they are, and when there is an error, they are corrected by the error correction circuit 104 according to the syndrome signal 108 and stored in the data register 101. If there is an error, the data stored in the data register 101 is corrected by an error correction code encoder (ECC ENC) in order to correct the data in the memory 310.
It is written in the memory 310 as data 213 ′ together with the error correction code 213 ″ generated in 102.

When the master processor 210 makes a read access, error correction has already been performed on the data register 10.
It is stored in 1. Therefore, the corrected data can be immediately supplied to the master processor 210 as the data 213. The master processor 210 terminates the read access at this point and moves to the execution of the next instruction. As described above, since the data reading from the memory 310 and the error correction operation are executed in advance based on the preceding operation of the pilot processor 220, the time from the start of the read access of the master processor 210 to the end of the read access. Can be shortened.

(2) Full-write access At the time of write access, there are two cases, one is to use the data 223 from the pilot processor 220 as the data to be written in the memory 310 and the other is to use the data 213 from the master processor 210. . Regardless of which method is used, the data to be written is written in the memory 310 as the data 213 ′ together with the error correction code 213 ″ generated by the error correction code encoder 102 through the data register 101.

When the data 223 from the pilot processor 220 is used as the data to be written in the memory 310, the error correction code encoder 102 can generate the error correction code prior to the access from the master processor 210. Can be faster. However, because pilot processor 220 operates without error correction, data 223 is more likely to be erroneous than data 213 from master processor 210. Therefore,
If the data 223 is incorrect, the data 21
If 3 is used, the reliability can be further improved.

On the other hand, when the data 213 from the master processor 210 is used as the data to be written in the memory 310, the full-write access has no merit of speeding up as compared with the conventional method, but as described above. If the data 223 is incorrect, the data 21
No ingenuity using 3 is required.

(3) Partial-write access The error correction code enables error correction of data having a larger number of bits with an error correction code having a smaller number of bits, and in order to improve bit utilization efficiency, one word unit or a plurality of words are used. Often generated in bytes. Therefore, it is necessary to generate the error correction code based on the data in units of one word or in units of a plurality of bytes even in the partial-write access in which only some of the bytes in one word are rewritten. In this case, some bytes of 1-word unit or plural bytes of data must be newly rewritten, and the remaining bytes must remain the same. Therefore,
It is necessary to read an entire word in advance in the data register 101, overwrite only the necessary bytes of data, generate an error correction code, and write it in the memory.

At the time of partial-write access, data 213 'and error correction code 213 "are output from memory 310 based on address 221 from pilot processor 220. Data 213' read from memory 310 and error correction code. Based on 213 "
The error correction code decoder 103 determines the presence / absence of an error and the syndrome (signal indicating the error bit position) 108.
If there is no error, the read data 212 'is stored as it is in the data register 101, and if there is an error, it is corrected by the error correction circuit 104 and stored in the data register 101. Here, only the necessary byte data is overwritten on the data stored in the data register 101, and is written in the memory 310 as the data 213 ′ together with the error correction code 213 ″ generated by the error correction code encoder 102. According to the present embodiment, the reading of the entire one word for the partial-write can be executed prior to the operation of the master processor 210, and accordingly, the speedup can be achieved.
In the case of writing, there are two cases in which data to be overwritten uses the data 223 from the pilot processor 220 and the data 213 from the master processor 210. Pilot processor 2
When the data 223 from 20 is used, the error correcting code can be generated by the error correcting code encoder 102 prior to the access from the master processor 210, so that the speed can be increased as compared with the conventional method. However, since the pilot processor 220 operates without error correction, data 2
The probability that 23 is incorrect is higher than the data 213 from the master processor 210. Therefore, if the data 223 is incorrect, if the data 213 is used instead, the reliability can be further improved.

On the other hand, when the data 213 from the master processor 210 is used, there is no merit of speeding up as compared with the conventional method, but when the data 223 as described above is erroneous, the data is replaced instead. No ingenuity such as using 213 is necessary.

The above-mentioned three types of access modes allow the master processor 210 to operate by a control signal 222 (not shown) including a signal indicating read / write discrimination from the pilot processor 220 and a signal indicating a byte size. It goes without saying that you can make decisions in advance.

FIG. 10 shows the address 21 from the master processor 210 and pilot processor 220 in the embodiment of FIG.
This is an embodiment in which the comparison and comparison circuits (CMP) 106 and 107 compare and collate 1, 221, data 213, and 223. Although not shown, it is also possible to compare and check the control signals 212 and 222 from the master processor 210 and the pilot processor 220.

In FIG. 11, the master processor 210 and the pilot processor 220 individually have memories 310.
And 320. The operation of this embodiment is basically the same as that of the embodiment shown in FIG. The difference between the two operations is that (1) the pilot processor 220 reads the data from the memory 320 without error correction in the embodiment of FIG. 2 during read access, and moves to the next operation (2).
In the embodiment of FIG. 2, the pilot processor 220 writes data to the memory 320 at the time of full-write access and at the time of partial-write access. According to the present embodiment, since the master processor 210 and the pilot processor 220 respectively use the memories 310 and 320 respectively, the frequency of occurrence of memory usage conflict between both processors in the embodiment of FIG. 1 does not decrease. , There is little decrease in operating speed due to competition.

FIG. 12 shows an embodiment in which addresses 211 and 221 and data 213 and 223 from the master processor 210 and pilot processor 220 are compared and compared by the comparison and comparison circuits 106 and 107 in the embodiment of FIG. Although not shown, the master processor 210
It is also possible to compare and check the control signals 212 and 222 from the pilot processor 220.

According to the embodiments shown in FIGS. 5 and 6, the errors in the memories 310 and 320 can be detected and corrected by the error correction code, and the outputs of both processors are compared and checked to thereby detect the error generated in the processors. Can also be detected. If the comparators described in Japanese Patent Application No. 6-27664 already invented by the inventors are used as the comparison and collation circuits (CMP) 106 and 107, the comparison and collation circuits (CMP) 10
Since 6, 107 themselves can be self-checking, the error detection rate can be increased.

Although the embodiment of the error correction code has been described above, the present invention can be similarly applied to the case of only error detection by parity or the like.

[0035]

According to the present invention, since the error correction circuit can be operated in advance by the signal from the pilot processor which operates in advance, error correction can be performed without applying overhead.

[Brief description of drawings]

FIG. 1 is a block diagram of an operation during read access.

FIG. 2 is a block diagram of an operation during write access.

FIG. 3 is a block diagram of an operation during read access with comparison check.

FIG. 4 is a block diagram of an operation during write access with comparison check.

FIG. 5 is an explanatory diagram of an operation according to a conventional technique.

FIG. 6 is an explanatory diagram of an operation according to the present invention.

FIG. 7 is an explanatory diagram of a conflict occurrence condition.

FIG. 8 is an explanatory diagram of an operation when a conflict occurs.

FIG. 9 is a block diagram of an example (shared memory) of a circuit configuration.

FIG. 10 is a block diagram of an example of a circuit configuration (shared memory, with comparison check).

FIG. 11 is a block diagram of a circuit configuration example (individual memory).

FIG. 12 is a block diagram of an example of a circuit configuration (individual memory, with comparison check).

[Explanation of symbols]

210 ... Master processor, 220 ... Pilot processor, 230 ... Error correction circuit, 310 ... Memory.

Claims (2)

[Claims] 1. A first processor for accessing the memory without error detection and correction, and a second processor for accessing the memory with error detection and correction, wherein the first processor is more than the second processor. Also executes the same instruction as the second processor in advance, the error detection and correction circuit for the second processor to access the memory with error detection and correction, the signal output by the first processor A fault-tolerant computer system, wherein the fault-tolerant computer system operates prior to the operation of the second processor. 2. The signal according to claim 1, wherein the signals output from the first processor and the second processor are compared with each other,
A fault-tolerant computer system that is considered abnormal if it does not match.