JPH0259843A - Memory device - Google Patents

Abstract

PURPOSE:To avoid the transformation of data by holding a serious fault error addresses in a writing mode to compare these error addresses with each other in a reading state and reporting the error to a system controller when the coincidence is obtained between the error addresses. CONSTITUTION:An error control circuit 16 holds an address when a serious fault error that is not reflected onto an error reply during a writing or partial writing action. A register 18 holds the detecting signal of the serious fault error. Then an AND circuit 20 sends an error reply to a system controller 11 via the circuit 16 when the coincidence is obtained between the address received from the controller 11 in a data reading state and the error address held by the register 18. Thus the occurrence of an error is reported to the controller 11 in case an error address is detected in a reading state. Then the error is processed and therefore the transformation of data can be avoided.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a storage device that returns an error reply to a system control device, and in particular, the present invention relates to a storage device that sends an error reply back to a system control device, and in particular, the present invention relates to a storage device that sends an error reply back to a system control device. This invention relates to a storage device having an error control function in case an error that is not reflected occurs.

[Conventional technology]

In a storage device in which data is written under the control of a system control device, if an error occurs in a write operation (write-related operation), an error reply is sent back to the system control device. This allows errors in write operations to be detected.

Furthermore, for errors that are not reflected in the error reply during write system operation, the errors are reported to the diagnostic control device, and the diagnostic control device performs error handling. That is, when the diagnostic control device receives an error that is not reflected in the error reply, it determines what type of error it is and then stops the system. On the other hand, if a storage device can prohibit writing, it prohibits write-related operations.

[Problem to be solved by the invention]

However, in such conventional storage devices, errors that are not reflected in the error reply are reported to the diagnostic control device.
After an error occurs and before the system stops,
Tens or hundreds of instructions are executed. If data at an address where an error has occurred is read during this time, the error will not be detected and the erroneous data will be treated as normal data, resulting in so-called garbled data.

[Means to solve the problem]

In the present invention, when a serious fault error that is not reflected in the error reply occurs during a write or partial write operation in the storage device, an error control circuit that holds the address at the time of the error and a detection signal of the serious fault error are provided. When the register to be held and the address sent from the system controller during data read operation match the error address held in the serious fault error hold register, an error reply is sent to the system controller via the error control circuit. It is characterized by having a sending AND circuit.

[Effect]

As a result, for serious fault errors that are not reflected in the error reply, the serious fault error and its error address are held, and if the address becomes an error address during a read operation, it is reported to the system control device and error handling is performed. , it is possible to prevent data corruption.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram of the storage device of the present invention, and FIG. 2 is a timing diagram showing the operation of each part thereof. Note that a timing signal check error will be explained as an example of a serious fault error.

First, a normal write operation is performed by manually inputting a request, command a, and address b from the system control 11 to the storage device 12. The request and command a are decoded by the main control circuit 13 of the storage device 12, and write operation control signals C1, C2, and C3 are sent to the timing control circuit 14, address control circuit 15, and error control circuit 16, respectively.
Sent to. In the timing control circuit 14, the control signal cl
, the RAS, CAS, and WE timing signals d are generated and sent to the memory matrix circuit 17, while the address b is input to the address control circuit 15 of the storage device 12, and is output as addresses e1 and C2 to the memory matrix circuit 17, respectively. It is sent to the error control circuit 16. In this case, although not shown, data is written to a specific address of the memory matrix circuit 17 in a write-related operation.

Here, if the address is a parity error etc. reply f
If an error occurs in time for the timing, an error reply g is sent back. However, the timing signal d
If there is a malfunction or the like, a timing error is detected by the error control circuit 16, and a serious fault error h is sent to the register 18.
is held. Further, the address at the time of this operation is held in a register in the error control circuit 16. At the timing of occurrence of serious error h, system control device 1
1: Return the error reply g: Until:'-
stomach. Therefore, the system control device 11 determines that the write operation has ended normally and continues processing.

Next: When a normal read operation is executed, address e1
Data is read from the address of the memory matrix circuit 17 specified by , and is sent to the system control device 11 (not shown). At this time, the comparison circuit 19 compares the error address 1 held in the write operation with the address e1 from the system control device 11, and if they match (5), outputs a logic value "1". Therefore, the output of the AND circuit 20 becomes the logical value "l", and the error control circuit 1
An error reply g is sent back via 6. If the addresses do not match, the error reply g will not be returned. When the error reply g is returned, the system control device 11
performs any necessary error handling.

〔Effect of the invention〕

As explained above, according to the present invention, when a serious fault error occurs during a write or partial write operation, the serious fault error and address are held, but the error is not reported to the system control device! Furthermore, since the error addresses are compared during the read operation and if they match, an error is reported to the system control device, it is possible to improve not only data integrity but also system reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the storage device of the present invention, and FIG. 2 is a timing diagram showing its operation. 11...System control device, 12...Storage device, 13...Main control circuit, 14...Timing control circuit, 15...
... Address control circuit, 16 ... Error control circuit, 17 ... Memory matrix circuit, 18 ...
...Register, 19...Comparison circuit, 0...
...AND circuit. Applicant NEC Corporation Representative Patent Attorney Umeo Yamauchi

Claims (1)

[Claims] When an error is detected in response to a write, read, or partial write command from the system control unit after executing a write, read, or partial write operation, and an error is detected in time to return a reply, an error reply is sent. an error control circuit that holds an address at the time of the error when a serious failure error that is not reflected in the error reply occurs during the write or partial write operation in the storage device configured to send data back to the system control device;
When an address sent from the system control device during a data read operation matches the error address held in the register, an error is detected via the error control circuit. A storage device comprising: an AND circuit that sends a reply to the system control device.