JPS6039249A - Operation device - Google Patents

Abstract

PURPOSE:To prevent an erroneous operation result from being written in a register by generating a parity by the result of operation of an operation section, storing the parity to a register, checking the parity and discriminating an error being a cause to an operation fault easily. CONSTITUTION:An LSI having an fault detecting function is provided with a data register 1 and an arithmetic logical operation circuit 2 as the operating section, the result of operation 7 obtained by the operation of the circuit 2 is inputted and provide a parity generation circuit 8 to generates a parity output 10. A parity output 10 from the circuit 8 is stored in a parity register 9 and output data 13, 14 of the register 9 are fed to parity check circuits 11, 12 by address signals 3, 4. The parity of the output data 5, 6 of the register 1 is checked by the circuits 11, 12 to output output signals 15 and 16, an output signal 18 of an OR circuit 17 as a control means controls the register 1 to prevent the write of the erroneous operation result to the register 1.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an arithmetic device having a fault detection function, especially a KLSI
This article relates to a computing device installed in an inn.

[Prior art]

FIG. 1 is a block diagram showing a conventional arithmetic device.

In the figure, 1 is a data register that stores data; 2 is a data register that stores data;
3.4 is an address signal that specifies the address of the data stored in the data register 1; and 5 is the address signal 3 that specifies the address. 6 is the output data read out from the data register 1 by specifying an address with the address signal 4, and 7 is the output signal of the ALU 2.

The conventional arithmetic unit is configured as described above, and the output data 5 or 6 read out from the data register 1 by the address specified by the address signal 3 or 4 is sent to the ALU 2.
Output to. Then, the result calculated by AI and U2 is outputted as an output signal 7, and then outputted as the address signal 4.
The data is stored at the address of data register 1 specified by .

However, since the conventional arithmetic unit is configured as described above, there is a problem in that when the arithmetic result of the ALU 2 is incorrect, it is extremely difficult to identify the faulty part. For example, in this conventional example, if the address of data register 1 specified by address signal 3 is faulty, the address of data register 1 specified by address signal 4 may be faulty, or if the address of data register 1 specified by address signal 4 is faulty.
There was a problem in that it was extremely difficult to determine whether the device was malfunctioning or not.

[Summary of the invention]

This invention was made by focusing on these problems.
A parity generation circuit that generates parity from the operation result obtained by the operation section, a parity register that stores the output data of the parity generation circuit, and a parity check using the output data of the parity register and the output data of the data register. By providing a parity check circuit for performing a parity check and a control means for controlling writing of the operation result to a data register according to an output signal of the parity check circuit, it is possible to easily identify a failure that causes an operation error. In addition, it is an object of the present invention to provide an arithmetic device that prevents erroneous arithmetic results from being written to a data register.

[Embodiments of the invention]

FIG. 2 is a block diagram showing an embodiment of the present invention,
1 to 7 are the same as the conventional device described above, so detailed explanations will be omitted. 8I'1 A parity generation circuit that generates parity from the operation result 7 of ALU2; 9 is a parity register that stores output data 10 of the parity generation circuit 8; 11.1
2 is a parity check circuit that performs a parity check using the output data 13.14 of the parity register 9 and the output data 5.6 from the data register 1, respectively; 15.16 is the respective parity check circuit 1;
1.12 output signal. 17 is its output signal 15.
16 is input in the OR circuit as a means of f[11,
A write control signal 18, which is an output signal of the OR circuit 17, controls writing of the calculation result 7 to the data register 1.

In the arithmetic unit configured as described above, output data 5 and 6 read from data register 1 in accordance with address signals 3 and 4 are input to ALU 2 and together with output data 13 and 14 of parity register 9, respectively).
The signal is input to the quality check circuits 11 and 12. A security check is carried out in each of the set and security check circuits 11 and 12, and output signals 15 and 16 are output to the outside. At the same time, the output signal 15°16 of the parity check circuit 11.12 is applied to the input terminal of the OR circuit 17.
is input, and a write control signal 18 is output from the OR circuit 17 to the data register 1 in accordance with the output signals 15 and 16 thereof.

In addition, the calculation result 7 of the ALU 2 is stored in the address of the data register 1 specified by the address signal 4 in accordance with the write control signal 18 input to the data register 1, and is also sent to the logic generation circuit 8. is input. Then, ten pieces of output data from the /CIJ property generation circuit 8 are stored at the address of the parity register 9 specified by the address signal 4.

For example, data (0010
)2 and data (0101)z are stored at address 1, and data (0101)z is stored at address 0 of parity register 9.
When "0" is stored as the parity of 010)2 and rlJ is stored as the parity of data (0101)2 at address 1, if you repeatedly perform the calculation to store 0 at address 0 and 1 at address 1, Then, the calculation result (0111
)2 is stored at address 1 of the data register 1, and the operation result (0
111) Parity “0” of 2 is 1 of parity register 9
Stored in address.

Here, if the operation result is stored as (0101)z due to a failure at address 1 of data register 1, and in the next operation, the data at addresses 0 and 1 are to be read out in the same way as described above, then 1 of data register 1 Parity check circuit 1
A parity error signal is input as an output signal 16 from the parity check circuit 12.

As a result, it is determined that the address of the data register 1 specified by the ATVS signal 4 is faulty. Also,
The parity error signal as the output signal 16 is input to the OR circuit 17, and the lifetime control signal 18 is inhibited so that the calculation result 7 is not written to the data register 1.

Note that the present invention is not limited to the scale of the data register and the functions of the arithmetic unit shown in the above embodiments, but can be applied to even larger scale data registers and even more multi-functional processors.
The present invention can also be applied to other parts of the body, and the same effects as those of the above-mentioned embodiments can be obtained.

〔Effect of the invention〕

As explained above, the present invention provides a parity generation system that generates parity from the operation result obtained by the operation part in an arithmetic unit that performs an operation using input data stored in a data register. a parity register that stores the output data of the parity generation circuit; a parity check circuit that performs a parity check using the output data of the parity register and the output data of the data register; By including the control means for controlling the writing of the calculation result to the data register, if the calculation result is incorrect, it is possible to easily determine which part is at fault, and also to prevent the incorrect calculation from occurring. This has the effect of preventing the result from being written to the data register. Therefore, it is expected that the failure rate of data registers will increase in the future as LSI density increases.
It is extremely effective in such cases.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional arithmetic device, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1... Data register 2... Arithmetic logic operation circuit as an arithmetic unit 5.6... Data register output data 7...
...Calculated polished rice obtained by the calculation section 8...
Parity generation circuit 9 Parity register 10 Parity generation circuit output data 11.12 Parity check circuit 13.1
4... Parity register output data 15.1
6... Output signal of parity check circuit 17... OR circuit 18 as control means...
・・・Control means output signal agent Masuo Oiwa

Claims (1)

[Claims] In an arithmetic device equipped with an arithmetic unit that performs an arithmetic operation using data stored in a data register, a high IJT generation circuit that generates parity from the arithmetic result obtained by the arithmetic unit and output data of the parity generation circuit are stored. a parity check circuit that performs a parity check using the output data of the parity register and the output data of the data register; The control means to control +ihλ
- An arithmetic device characterized by the following.