JPS59152600A - Microcomputer - Google Patents

Abstract

PURPOSE:To detect quickly the occurrence of a trouble in a data memory, by comparing the parity of data, which is read out when data is read out from a data memory part, with the parity of parity data and outputting an abnormality occurrence signal when they do not coincide with each other. CONSTITUTION:Data is inputted from a data bus 4 to a parity generating circuit 10, and it is discriminated whether its partity is ''1'' or ''0'', and data including parity data is inputted to a data memory 9 and is stored in an area designated by an address bus 8. In case of data read, data in the area designated by the address bus 8 is inputted to the parity generating circuit 10 similarly to write, and the parity is discriminated. It is discriminated whether the output of the parity generating circuit 10 and parity data in the data memory 9 coincide with each other or not, that is, whether the output of a discriminating circuit 11 is ''0'' or ''1''. Thus, even if an abnormality occurs in the data memory of a microcomputer, it is detected easily.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a microcomputer.

[Prior art]

As is well known, a microcomputer has an arithmetic logic unit (ALU) and a read-only memory (ROM).

It is a semiconductor integrated circuit device composed of a readable/writable memory (RAM), a control circuit, and the like.

FIG. 1 is a block diagram of the main parts of an example of a conventional microcomputer.

In this microcomputer, instruction codes and numerical data for performing a series of tasks are stored in memory such as program memory (ROM) 2 or data memory (RAM) 3, and are stored in memory such as a program counter or registers for storage and processing. The memory contents at the address specified via the address bus 8 are output to the data bus 4 according to the contents of the register 1 configured by the register 1, are processed by the arithmetic circuit 6, and then are the memory contents specified by the address bus 8 again. Stored in memory at address.

In such a microcomputer, if at least a part of the readable/writable memory IJ (RAM) no longer functions adequately due to some fault,
The process will be executed according to the problem. In other words, a program different from the program that should be executed is executed. When a microcomputer is used in an important device, it is necessary to quickly detect the occurrence of malfunctions due to problems with the RAM.

However, conventional microcomputers have the disadvantage that there is no method for detecting the occurrence of a malfunction in the RAM, and that even if a malfunction occurs due to malfunction, it is not easy to detect it.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer that eliminates the above-mentioned drawbacks and is capable of quickly detecting the occurrence of a RAM failure.

[Structure of the invention]

The microcomputer of the present invention includes a data memory section to which a parity data bit is added for simultaneously storing stringity data when data is stored, and a memory section for determining when the parity data is written to and read from the parity data bit. It is configured to include a generation circuit and a comparison circuit that compares the parity of the read data and the parity of the quality data when reading data from the previous data memory section, and outputs an abnormality occurrence signal when there is a mismatch. .

[Explanation of Examples]

Next, embodiments of the present invention will be described using the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention.

The microcomputer of this embodiment includes a data memory section 9 to which parity data bits are added for storing parity data at the same time as data is stored, and a determination when writing and reading the parity data to and from the parity data bits. The parity generating circuit 10 includes a parity generation circuit 10 that performs the above operations, and a comparison circuit 11 that compares the parity of the data read out when reading data from the data memory section 9 with the parity of the parity data, and outputs an abnormality signal when there is a mismatch. Consists of.

To explain in more detail, the data memory (RAM) 9 has one more bit added to the data length compared to the data memory IJ(l(AM)3) shown in FIG. 1, and parity data is stored in this additional bit. .Data memo IJ
When writing data to (RAM) 9, the data is input from the data bus 4 to the parity generation circuit 10, and the parity generation circuit 10 determines whether the /NOIJ value of the input data is ``1'' or ``0''. Then, the data including the parity data is input to the data memory (RAM) 9.

Data including parity data is stored in an area of data memory (R, AM) 9 designated by address bus 8. When reading data from data memory (RAM) 9, the data in the area specified by address bus 8 is input to parity generation circuit 10 in the same way as when writing. The parity generation circuit 10 determines the parity of input data in the same way as when writing. and data memory (R
The determination circuit 11 compares the parity data with the parity data output from the AiVl) 9. Paridy generation circuit 10
If the output of the data memo IJ (RAM) 9 matches, it is normal, and if they do not match, it can be detected that an abnormality has occurred in the data memo IJ (RAM) 9. Therefore, by determining whether the output of the determination circuit 11 is ``0'' or 1'', even if an abnormality occurs in the data memory (RAM) of the microcomputer, it can be easily detected, and important equipment can be kept safe. It can be applied with care.

〔Effect of the invention〕

As described above in detail, according to the present invention, it is possible to obtain a microcomputer that can quickly detect a problem even if a problem occurs in a data memory, which is highly effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of an example of a conventional microcomputer, and FIG. 2 is a block diagram of the main parts of an embodiment of the present invention. 1...Register, 2.Song/program memory (
RlOM), -3...Data memory (RAM)
, 4... Song data bus, 5... Input/output circuit, 6
...A curved arithmetic circuit. 7...Instruction decoder, 8...
... Address bus, 10 ... Parity generation circuit, 11 ... Judgment circuit.

Claims (1)

[Claims] a data memory section with a parity data bit that stores parity data at the same time as data is stored;
A parity generation circuit that makes a determination when writing and reading the parity data to and from the parity data bit, and a parity generating circuit that compares the parity of the read data and the parity of the parity data when reading data from the data memory section. A microcomputer comprising: a comparison circuit that outputs an abnormality signal when there is a mismatch.