JPS5868299A - Detecting circuit for address fault - Google Patents

Abstract

PURPOSE:To stop operation before the occurrence of a fault by providing a CPU, a program storage memory, a data storage memory, an address line, an address storage means, and a coincidence circuit for address comparison, and thus detecting an address fault. CONSTITUTION:Address data from a CPU1 are supplied to memories 5 and 6 through an address line 2 and address latch circuit 4. A data line 3 is also led out of the CPU1. In a large-scale system, they are connected to memories 15- 17 of memory devices 18-20 through buffer gates 7-14. If a buffer gate has a fault, addresses with the same pattern are outputted. For this purpose, a memory device 40 having a memory 22 and buffer gates 21 and 23 is provided with said address storage means 30 and a coincidence circuit for comparing a last address with a current address and when the same address is detected successively, a decision on a fault is made to output a fault signal A to the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address abnormality detection circuit C for an address bus of a computer system or a microcomputer.

A central processing unit (hereinafter referred to as CPU) that performs data processing and arithmetic processing, a memory device that stores a program for performing specified operations, and a memory device that stores data for program processing. When each memory is assigned an address (;, the CPU operates by specifying an address using the address line, fetching an instruction from the memory that stores a program, or executing an instruction). Data is processed. In this case, an address for fetching an instruction word and an address for executing an instruction are output from the CPU via the address line.

However, similar to the data lines, the address line may also suffer from abnormality. Conventionally, data line problems have been prevented by parity checks and the like. However, in most conventional address lines, no protection measures have been taken.

The main purpose of the present invention is to detect this address abnormality, which has not been done in the past, by comparing one address with the current address.

An embodiment of the present invention will be described below with reference to the drawings.

Figure W7IJ1 is a block diagram showing a general connection method for a CPU device and a memory device. The address output from the CPU 1 is sent to each memory 5.6 as address data via an address line 2 and an address latch circuit 4.
1 knee connected.

3 is a data line. In a small-scale system, the memory C can be directly connected as an address line, but in a large-scale system, the load becomes heavy and the memory devices 1B, 19 .
It is connected to 20 memories 15, 16, and 17. If a failure occurs in the buffer gate circuit at this time, addresses of the same pattern are often output to the memories below it. In a system where the address line output from the CPU is connected to several memory devices 1:@ via a buffer gate, etc., if the buffer gate in the memory device fails, the general (two-same-failure mode) occurs. Even if the address output from the CPU changes, the address in the memory device does not change.Also, as shown in Fig. to detect address anomalies.

FIG. 2 shows a block diagram of a memory device according to an embodiment of the present invention. This memory device 40 corresponds to the memory devices 18 to 20 in FIG. 21.

23 is a buffer gate, and 22 is a memory.

30 is means for storing the previous address, and 31 is a matching circuit for comparing the previous address and the current address.

That is, an address matching circuit is provided in the address line between the final stage gate and the memory, and when the address line matches one address, a fault signal A is output to the CPU as an address line fault.

As described above, in the present invention, the address line output from the central processing unit is connected to the buffer gate by taking advantage of the fact that in a general computer system, the program progresses sequentially (the same address is never accessed consecutively). In a device that is connected to multiple memory devices via a memory device, each memory device is equipped with an address matching circuit, and if the same address is detected consecutively, an abnormal signal is sent to the CPU as an abnormality, resulting in an abnormal calculation result. C2, the computer can be stopped before an abnormal state of the computer occurs.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating a general computer system, and FIG. 2 is a block diagram illustrating a memory device according to an embodiment C2 of the present invention. 30... Means for storing addresses 31... Address matching circuit agent Patent attorney Norichika Kensuke (1 idiot) Figure 1

Claims (1)

[Claims] A central processing unit that performs arithmetic processing, a memory device that stores a program that causes the central processing unit to perform predetermined operations, another memory device that stores data for program processing, and the allocation of these memory devices. an address line for transmitting an address signal specifying a memory device for retrieving information from or storing information by an address assigned to the memory device; a means for storing a previous address; 1. An address abnormality detection circuit comprising: a matching circuit that compares a current address with a current address, and detects an address abnormality.