JPS5827538B2 - Mutual monitoring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an abnormality detection method for a composite processor system having a plurality of processors, and particularly to a mutual monitoring method in which a pair of silk processors mutually monitors the processors.

In a general-purpose composite processor system that includes a plurality of processors and provides an environment in which they work in conjunction with each other, a means for detecting an abnormality in any processor and notifying the other processors is essential.

In the absence of such a means, a normal processor may continue to work as if the abnormal processor were normal, and the system as a whole may perform erroneous operations that are completely meaningless.

In order to prevent such a situation, it is desirable that a plurality of processors mutually check for abnormalities in other processors.

In systems dedicated to specific tasks, this check is usually built into the program, but in general-purpose complex processor systems, such as those mentioned at the beginning of this section, the above method is highly program-dependent; This cannot be set in advance.

However, in a general-purpose composite processor system, at least means for constantly monitoring whether or not a processor has stopped abnormally should be provided as part of the system in order to isolate and recover an abnormal processor.

Conventionally, for simplicity, a method has been generally used in which one of a plurality of processors is used as a management processor to directly access other working processors and check information.

The drawback of this method is that all abnormality checking functions stop due to a failure of the management processor.

Some methods have been used in which processors mutually check for abnormalities, but directly accessing a faulty processor may cause a deadlock among normal processors or change the state of a processor that is stopped due to a fault. cause
It can make recovery operations difficult and has the disadvantage that the processors must be configured to allow direct processor-to-processor access.

SUMMARY OF THE INVENTION An object of the present invention is to provide a mutual monitoring force formula that allows mutual monitoring to be easily performed between any two processors.

Another object of the present invention is to provide a mutual monitoring system that, when a processor abnormally stops, allows the other party to easily know in which phase of processing the abnormality occurred, thereby facilitating recovery processing.

Still another object of the present invention is to provide a mutual monitoring system that can use general processors by adding a monitoring relay device as an input/output device without using a special processor.

According to the present invention, a composite processor system including a plurality of processors includes a monitoring relay device corresponding to a pair of two processors that attempt to monitor each other, and the monitoring relay device performs mutual monitoring. The processor is connected so that it can be accessed by two processors, and only when the code given by the processor matches the code held in the monitoring relay device during monitoring access from the processor, a normal message is sent to the accessed processor. each of the pair of processors performing the mutual monitoring includes means for returning a signal and controlling the code held in the monitoring relay device to be replaced with the next code according to a first predetermined order;
performing monitoring access to the monitoring relay device with second and third codes in a predetermined order selected by a certain algorithm from the code string in the first predetermined order; A mutual monitoring system is obtained in which an abnormality in a mutually monitoring partner processor is known by detecting the absence of the normal signal.

In the mutual monitoring system according to the present invention, two processors that perform mutual monitoring receive a code string (for example, A, B, C,...) that appears in the monitoring register in a first predetermined order.
Z, A, B...), the first processor (for example, A) is the first processor of the two processors mentioned above, the second processor (for example, B) is the second processor, and so on. However, the second and third code strings (for example, A, C
,E.

..., Y, A... and B, D, F,..., Z,
With the codes sequentially extracted from B...), monitoring access is made to the monitoring relay device alternately at regular intervals.

If there is no error in the above code string, the contents of the monitoring register are changed according to the first order, and the contents of the monitoring register always match the code strings given by the first and second processors upon monitoring access. , a normal signal is returned to both of the second processors, but if one of the two processors fails and access to the monitoring device stops, the contents of the monitoring register and the information given at the time of monitoring access are returned. If a mismatch occurs with the code, it is possible to immediately return an abnormality signal to notify the other party that the other party's processor has malfunctioned and stopped.

Furthermore, if the processor that receives the abnormal signal reads the contents of the monitoring register, it can easily know from which part of the process it should retry based on the code.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an overall diagram of an embodiment of the present invention, in which a first processor 1011, a second processor 1012, and a monitoring relay device 100, which perform mutual monitoring, are coupled by an I10 bus 102.

FIG. 2 shows the interception of the monitoring relay device 100 and the monitoring register 120 by the controller 110.8 bit counter.
, the comparator 130 and the I10 bus 102 are connected by a control bus 112, a register bus 122, and a data bus 132, and the comparator 130 and the monitoring register 120 are connected by a comparison bus 123.

The controller 110 has a function similar to that of a normal I10 device controller, but in particular has a test-and-set function when the device is busy based on a monitoring access command.It can respond normally/abnormally based on the comparison result of the monitoring register 120 and the data on the data bus 132 by the comparator 130. It also has the function of counting up the contents of the monitoring register if it is normal.

That is, in this embodiment, the code strings according to the first predetermined order are 0.1, 2, . ...255,0,1
,2. The controller 110 increments the contents of the monitor register 120 by one when the normal response condition is satisfied by the monitor access command.

Mutual monitoring in this embodiment is performed in the following steps.

The first processor 1011 sends an initialize command to the monitoring relay device 100, and subsequently interrupts the second processor 1012 in the waiting state, thereby causing the second processor to start monitoring access, and After approximately half the time of the monitored access interval, the first
The processor 101□ itself also starts monitoring access.

Upon receiving the initialization command, the controller 110 of the monitoring relay device 100 enters the initial state, energizes the reset control line 140, and clears the monitoring register 120.

The second processor 101□ performs monitoring access every 10 msec, but the codes output by the monitoring access are 0,
2,4. ...254.0..., and the first processor 101 also performs monitoring access every 10 msec, and the codes output by the monitoring access are 1, 3, 5, . ...255,1. The order is...

The first monitoring access to the monitoring relay device 100 consists of a monitoring access command and a sense command, which are successively executed by the second processor 1012.
The data sent by the supervisory access command II
It is OII.

When the controller 110 of the monitoring relay device 100 that received the previous monitoring access command receives the monitoring access command via the control bus 112, it changes the internal state that was ready to busy, and causes the comparator 130 to read the contents of the monitoring register 120, i.e. ”□ II and contents of data bus 132 “0
11, and upon receiving a match signal 142 as a result of the comparison, it enters a normal response mode, energizes the count line 141, and increases the contents of the monitoring register 120.

Upon receiving the sense command issued following the monitoring access command, the controller 110 in the normal response mode sends a normal signal to I10 through the control bus 112.
It is sent onto the bus 102 and released from the busy state.

By the processor 1011 of the apprentice 1, the code “I If
Monitoring access is performed with
The operation of 10 is the same as above, and the contents of monitor register 120 are further increased to 1121+.

Since the first and second processors 1011 and 1012 perform monitoring access alternately at the same fixed time interval, the monitoring relay device 100 operates normally unless either of the two processors 1011 or 1012 stops abnormally. Repeat the response.

Let us now consider the case where the second processor abnormally stops after the supervisory access with code 1125011.

In this case, the contents of the monitoring register 120 are l+25111
112 of the first processor 1o11
511+, a normal response is returned, and the result is II, 25.211, but furthermore, a normal response is not returned to the monitoring access with the code I+ 25311 of the e-first processor 101. do not have.

That is, although the controller 110 of the monitoring relay device 100 is busy receiving the monitoring access command, the content 112521+ of the monitoring register 120 and the content I+ 2531+ on the data bus 132 do not match, and the comparator 130 receives the match signal 142. Since the controller 110 is not energized, the controller 110 does not enter the normal response mode, and when the controller 110 skips to the subsequent sense command, it only releases the busy state but does not return a normal response.

Through the above operations, the first processor 1011 learns that the second processor 1012 has stopped abnormally, and if necessary, sends a monitor register read command to the controller 110.
This causes the code I+ 25211 in the supervisory register 120 to be sent, thereby knowing that the second processor 101□ was working normally until the supervisory access with the code I+ 2501+.

The method of obtaining the constant time interval may be, for example, by using a timer device of the processor and an interrupt, and the fine time difference between two processors is determined by the timer device when the supervisory access command is issued. This may be detected and corrected by repeating the error signal and the device returns busy, or it may be determined that it is abnormal only after receiving the abnormal signal twice, but these are all well-known methods, and no further action will be taken. I won't say it.

As explained above, according to the present invention, mutual monitoring between processors can be easily performed, the processing phase when an abnormality occurs can be easily known, and the monitoring register from the processor can be easily monitored. Since writing is not allowed, a mutual monitoring system is obtained in which the contents of the monitoring register are not destroyed even by an abnormality in the processor.

This is accessed exclusively by the first and second processors, and returns a normal response only when the code given at the time of access matches the contents of the monitoring register, and replaces the contents of the register with a code according to a predetermined order. The method relies on the installation of a controlled monitoring relay device and the method in which the first and second processors alternately access said monitoring relay device at the same constant time interval and with codes according to a predetermined order. There is.

[Brief explanation of the drawing]

FIG. 1 is an overall diagram of an embodiment of the present invention, and FIG. 2 is a configuration diagram of a monitoring relay device. 1011.101□・・・Processor, 102...
...I10 bus 100 ... Monitoring relay device, 110 ... Controller, 120 ...
- Monitoring register, 130... Comparator.

Claims (1)

[Claims] 1. A composite processor system consisting of a plurality of processors has a monitoring relay device corresponding to a pair of two processors that monitor each other, and the monitoring relay device is accessed by the two processors that monitor each other. When a code given by a processor matches a code held in the monitoring relay device when a processor makes a monitoring access, a normal signal is returned to the accessed processor and a signal is sent to the monitoring relay device. control means for replacing the stored codes with codes according to a first predetermined order, and each of the pair of processors performing the mutual monitoring each replaces a code string according to the first predetermined order. Monitoring access is performed to the monitoring relay device with codes according to a second and third predetermined order selected using a more constant algorithm, and an abnormality in the mutually monitoring partner processor is detected by detecting a lack of the normal signal. A mutual monitoring method characterized by knowing the following information.